Nexus Development Interface (NDI) RM0046
888/936 Doc ID 16912 Rev 5
36.12 External Debug Support
External debug support is supplied through the e200z0h OnCE controller serial interface
which allows access to internal CPU registers and other system state while the CPU is
halted in debug mode. All debug resources including DBCR0–4, DBSR, IAC1–4, DVC1–2,
DAC1–2 are accessible through the serial OnCE interface in external debug mode. Setting
the DBCR0
EDM
bit to ‘1’ through the OnCE interface enables external debug mode, and
unless otherwise permitted by the settings in DBERC0, disables software updates to the
debug registers. When DBCR0
EDM
is set, debug events enabled to set respective DBSR
status bits will also cause the CPU to enter Debug Mode as opposed to generating Debug
Interrupts, unless the specific events are allocated to software via the settings in DBERC0.
In Debug Mode, the CPU is halted at a recoverable boundary, and an external Debug
Control Module may control CPU operation through the On-Chip Emulation logic (OnCE).
Note: On the initial setting of DBCR0
EDM
to ‘1’, other bits in DBCR0 will remain unchanged. After
DBCR0
EDM
has been set, all debug register resources may be subsequently controlled
through the OnCE interface. The DBSR register should be cleared as part of the process of
enabling external debug activity. The CPU should be placed into debug mode via the
OCR
DR
control bit prior to writing EDM to ‘1’. This gives the debugger the opportunity to
cleanly write to the DBCRx registers and the DBSR to clear out any residual state / control
information which could cause unintended operation.
Note: It is intended for the CPU to remain in external debug mode (DBCR0
EDM
=1) in order to
single step or perform other debug mode entry/ reentry via the OCR
DR
, by performing
go+noexit commands, or by assertion of the jd_de_b signal.
Note: DBCR0
EDM
operation will be blocked if OnCE operation is disabled (jd_en_once negated)
regardless of whether it is set or cleared. This means that if DBCR0
EDM
was previously set,
and then jd_en_once is negated (this should not occur), entry into debug mode will be
blocked, all events are blocked, and watchpoints are blocked.
Due to clock domain design, the CPU clock (m_clk) must be active in order to perform
writes to debug registers other than the OnCE Command register (OCMD), the OnCE
Control register (OCR), or the DBCR0
EDM
bit. Register read data is synchronized back to
the j_tclk clock domain. The OnCE Control register provides the capability of signaling the
system level clock controller that the CPU clock should be activated if not already active.
Updates to the DBCRx and DBSR registers via the OnCE interface should be performed
with the CPU in debug mode to guarantee proper operation. Due to the various points in the
CPU pipeline where control is sampled and event handshaking is performed, it is possible
that modifications to these registers while the CPU is running may result in early or late
entry into debug mode, and may have incorrect status posted in the DBSR register.
If resource sharing is enabled via DBERC0, updates to the DBERC0, DBCRx, and DBSR
registers must
be performed with the CPU in debug mode, since simultaneous updates of
register portions could otherwise be attempted, and such updates are not guaranteed to
properly occur. The results of such an attempt are undefined
.
36.12.1 OnCE Introduction
The e200z0h on-chip emulation circuitry (OnCE™/Nexus Class 1 interface) provides a
means of interacting with the e200z0h core and integrated system so that a user may
examine registers, memory, or on-chip peripherals facilitating hardware/software
development. OnCE operation is controlled via an industry standard IEEE 1149.1 TAP
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