ST SPC560P34 - Figure 287. Interrupt Status Register (ISR); Interrupt Registers

RM0046 Analog-to-Digital Converter (ADC)
Doc ID 16912 Rev 5 591/936
Note: MSR[JSTART] is automatically set when the injected conversion starts. At the same time
MCR[JSTART] is reset, allowing the software to program a new start of conversion.
The JCMR registers do not change their values.
23.4.3 Interrupt registers
Interrupt Status Register (ISR)
The Interrupt Status Register (ISR) contains interrupt status bits for the ADC.
CTUSTART This status bit is used to signal that a CTU conversion is ongoing.
CHADDR
Current conversion channel address
This status field indicates current conversion channel address.
ACKO
Auto-clock-off enable
This status bit is used to signal if the Auto-clock-off feature is on.
ADCSTATUS
The value of this parameter depends on ADC status:
000 IDLE — The ADC is powered up but idle.
001 Power-down — The ADC is powered down.
010 Wait state — The ADC is waiting for an external multiplexer. This occurs only when the DSDR
register is non-zero.
011 Reserved
100 Sample — The ADC is sampling the analog signal.
101 Reserved
110 Conversion — The ADC is converting the sampled signal.
111 Reserved
Table 296. MSR field descriptions (continued)
Field Description
Figure 287. Interrupt Status Register (ISR)
Address: Base + 0x0010 Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000 000
EO
CTU
JEOC JECH
EOC ECH
W
w1c w1c w1c w1c w1c
Reset0000000000000000