Interrupt Controller (INTC) RM0046
208/936 Doc ID 16912 Rev 5
9 Interrupt Controller (INTC)
9.1 Introduction
The INTC provides priority-based preemptive scheduling of interrupt service requests
(ISRs). This scheduling scheme is suitable for statically scheduled hard real-time systems.
The INTC supports 128 interrupt requests. It is targeted to work with Power Architecture
technology and automotive applications where the ISRs nest to multiple levels, but it also
can be used with other processors and applications.For high-priority interrupt requests in
these target applications, the time from the assertion of the peripheral’s interrupt request to
when the processor is performing useful work to service the interrupt request needs to be
minimized. The INTC supports this goal by providing a unique vector for each interrupt
request source. It also provides 16 priorities so that lower priority ISRs do not delay the
execution of higher priority ISRs. Because each individual application will have different
priorities for each source of interrupt request, the priority of each interrupt request is
configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that tasks
sharing the resource will not preempt each other.
Multiple processors can assert interrupt requests to each other through software
configurable interrupt requests. These software configurable interrupt requests can also be
used to separate the work involved in servicing an interrupt request into a high-priority
portion and a low-priority portion. The high-priority portion is initiated by a peripheral
interrupt request, but then the ISR can assert a software configurable interrupt request to
finish the servicing in a lower priority ISR. Therefore these software configurable interrupt
requests can be used instead of the peripheral ISR scheduling a task through the RTOS.
9.2 Features
● Supports 120 peripheral interrupt and 8 software-configurable interrupt request
sources
● Unique 9-bit vector per interrupt source
● Each interrupt source programmable to one of 16 priorities
● Preemption
– Preemptive prioritized interrupt requests to processor
– ISR at a higher priority preempts ISRs or tasks at lower priorities
– Automatic pushing or popping of preempted priority to or from a LIFO
– Ability to modify the ISR or task priority; modifying the priority can be used to
implement the priority ceiling protocol for accessing shared resources.
● Low latency—3 clock cycles from receipt of interrupt request from peripheral to
interrupt request to processor
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