ST SPC560P34 - Module Features; High Performance E200 Z0 Core Processor

RM0046 Introduction
Doc ID 16912 Rev 5 53/936
● Interrupts and events
– 16-channel eDMA controller
– 16 priority level controller
– Up to 25 external interrupts
– PIT implements four 32-bit timers
– 120 interrupts are routed via INTC
● General purpose I/Os
– Individually programmable as input, output or special function
– 37 on LQFP64
– 64 on LQFP100
● 1 general purpose eTimer unit
– 6 timers each with up/down capabilities
– 16-bit resolution, cascadeable counters
– Quadrature decode with rotation direction flag
– Double buffer input capture and output compare
● Communications interfaces
– 2 LINFlex channels (1 × Master/Slave, 1 × Master Only)
– Up to 3 DSPI channels with automatic chip select generation (up to 8/4/4 chip
selects)
– 1 FlexCAN interface (2.0B Active) with 32 message buffers
– 1 safety port based on FlexCAN with 32 message buffers and up to 8 Mbit/s at
64 MHz capability usable as second CAN when not used as safety port
● One 10-bit analog-to-digital converter (ADC)
– Up to 16 input channels (16 ch on LQFP100 and 12 ch on LQFP64)
– Conversion time < 1 s including sampling time at full precision
– Programmable Cross Triggering Unit (CTU)
– 4 analog watchdogs with interrupt capability
● On-chip CAN/UART bootstrap loader with Boot Assist Module (BAM)
● 1 FlexPWM unit
– 8 complementary or independent outputs with ADC synchronization signals
1.6 Module features
1.6.1 High performance e200z0 core processor
The e200z0 Power Architecture core provides the following features:
● High performance e200z0 core processor for managing peripherals and interrupts
● Single issue 4-stage pipeline in-order execution 32-bit Power Architecture CPU
● Harvard architecture
● Variable length encoding (VLE), allowing mixed 16- and 32-bit instructions
– Results in smaller code size footprint
– Minimizes impact on performance