Deserial Serial Peripheral Interface (DSPI) RM0046
478/936 Doc ID 16912 Rev 5
20.8.7 Interrupts/DMA requests
The DSPI has conditions that can generate interrupt requests only, and conditions that can
generate interrupts or DMA requests. Table 229 lists these conditions.
Each condition has a flag bit and a request enable bit. The flag bits are described in the
Section , “DSPI Status Register (DSPIx_SR) and the request enable bits are described in
the Section , “DSPI DMA / Interrupt Request Select and Enable Register (DSPIx_RSER).
The TX FIFO fill flag (TFFF) and RX FIFO drain flag (RFDF) generate interrupt requests or
DMA requests depending on the TFFF_DIRS and RFDF_DIRS bits in the DSPIx_RSER.
End of queue interrupt request (EOQF)
The end of queue request indicates that the end of a transmit queue is reached. The end of
queue request is generated when the EOQ bit in the executing SPI command is asserted
and the EOQF_RE bit in the DSPIx_RSER is set. Refer to the EOQ bit description in
Section , “DSPI Status Register (DSPIx_SR). Refer to Figure 220 and Figure 221 that
illustrate when EOQF is set.
Transmit FIFO fill interrupt or DMA request (TFFF)
The transmit FIFO fill request indicates that the TX FIFO is not full. The transmit FIFO fill
request is generated when the number of entries in the TX FIFO is less than the maximum
number of possible entries, and the TFFF_RE bit in the DSPIx_RSER is set. The
TFFF_DIRS bit in the DSPIx_RSER selects whether a DMA request or an interrupt request
is generated.
Transfer complete interrupt request (TCF)
The transfer complete request indicates the end of the transfer of a serial frame. The
transfer complete request is generated at the end of each frame transfer when the TCF_RE
bit is set in the DSPIx_RSER. Refer to the TCF bit description in Section , “DSPI Status
Register (DSPIx_SR). Refer to Figure 220 and Figure 221, which show when TCF is set.
Transmit FIFO underflow interrupt request (TFUF)
The transmit FIFO underflow request indicates that an underflow condition in the TX FIFO
has occurred. The transmit underflow condition is detected only for DSPI modules operating
in slave mode and SPI configuration. The TFUF bit is set when the TX FIFO of a DSPI
Table 229. Interrupt and DMA request conditions
Condition Flag Interrupt DMA
End of transfer queue has been reached (EOQ) EOQF X
TX FIFO is not full TFFF X X
Current frame transfer is complete TCF X
TX FIFO underflow has occurred TFUF X
RX FIFO is not empty RFDF X X
RX FIFO overflow occurred RFOF X
A FIFO overrun occurred
(1)
TFUF ORed with RFOF X
1. The FIFO overrun condition is created by ORing the TFUF and RFOF flags together.
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