ST SPC560P34 - Figure 440. Fake Fault Generation Register (FCU_FFGR); Table 404. FCU_FFFR Field Descriptions; Table 405. FCU_FFGR Field Description

Fault Collection Unit (FCU) RM0046
764/936 Doc ID 16912 Rev 5
Table 404 provides a detailed bit description. Ta bl e 40 3 provides a detailed list of
recoverable faults.
Fake Fault Generation Register (FCU_FFGR)
The FCU_FFGR allows the user to emulate a software/hardware recoverable fault in order
to test the FCU logic. Once a bit in the FCU_FFGR is set, the FCU should behave exactly in
the same way after detecting a real fault. This register can be accessed only when Test
mode is entered (check TM field in FCU_MCR). In Test mode, real faults are not detected
and fake faults for SRF0 and SRF1 cannot be generated.
Table 404. FCU_FFFR field descriptions
Field Description
0:4
FRSRF0–
FRSRF4
Software Recoverable Fault
0: No error latched
1: Error latched
16:31
FRHRF15
–
FRHRF0
Hardware Recoverable Fault
0: No error latched
1: Error latched
Figure 440. Fake Fault Generation Register (FCU_FFGR)
Address: Base + 0x000C Access: User read/write, Supervisor read/write
0123456789101112131415
R
FSRF
0
FSRF
1
FSRF
2
FSRF
3
FSRF
4
00000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
FHRF
15
FHRF
14
FHRF
13
FHRF
12
FHRF
11
FHRF
10
FHRF
9
FHRF
8
FHRF
7
FHRF
6
FHRF
5
FHRF
4
FHRF
3
FHRF
2
FHRF
1
FHRF
0
W
Reset0000000000000000
Table 405. FCU_FFGR field description
Field Description
0:4
FSRF0–
FSRF4
Fake Software Recoverable Fault[0:4]
0: No error latched
1: Error latched
16:31
FHRF15–
FHRF0
Fake Hardware Recoverable Fault[15:0]
0: No error latched
1: Error latched