Analog-to-Digital Converter (ADC) RM0046
586/936 Doc ID 16912 Rev 5
The analog watchdog interrupts are handled by two registers WTISR (Watchdog Threshold
Interrupt Status Register) and WTIMR (Watchdog Threshold Interrupt Mask Register) in
order to check and enable the interrupt request to the INTC module. The Watchdog interrupt
source sets two pending bits WDGxH and WDGxL in the WTISR for each of the channels
being monitored.
Note: In order to reduce the number of interrupt lines, EOC, ECH, JEOC, JECH and EOCTU are
combined (OR-ed) on the same line ADC_EOC, and WDG0L, WDG0H, WDG1L, WDG1H,
WDG2L, WDG2H, WDG3L and WDG3H are combined (OR-ed) on the same line ADC_WD.
According to this, the total number of interrupt lines is 2. If the ADC is in CTU Control Mode,
only the sources EOCTU, WDG0L, WDG0H, WDG1L, WDG1H, WDG2L, WDG2H, WDG3L
and WDG3H can generate an interrupt request.
23.3.8 Power-down mode
The analog part of the ADC can be put in low power mode by setting the MCR[PWDN]. After
releasing the reset signal the ADC analog module is kept in power-down mode by default,
so this state must be exited before starting any operation by resetting the appropriate bit in
the MCR.
The power-down mode can be requested at any time by setting the MCR[PWDN]. If a
conversion is ongoing, the ADC must complete the conversion before entering the power
down mode. In fact, the ADC enters power-down mode only after completing the ongoing
conversion. Otherwise, the ongoing operation should be aborted manually by resetting the
NSTART bit and using the ABORTCHAIN bit.
MSR[ADCSTATUS] bit is set only when ADC enters power-down mode.
After the power-down phase is completed the process ongoing before the power-down
phase must be restarted manually by setting the appropriate MCR[START] bit.
Resetting MCR[PWDN] bit and setting MCR[NSTART] or MCR[JSTART] bit during the same
cycle is forbidden.
If a CTU trigger pulse is received during power-down, it is discarded.
If the CTU is enabled and the MSR[CTUSTART] bit is ‘1’, then the MCR[PWDN] bit cannot
be set.
23.3.9 Auto-clock-off mode
To reduce power consumption during the IDLE mode of operation (without going into power-
down mode), an “auto-clock-off” feature can be enabled by setting the MCR[ACKO] bit.
When enabled, the analog clock is automatically switched off when no operation is ongoing,
that is, no conversion is programmed by the user.
Note: The auto-clock-off feature cannot operate when the digital interface runs at the same rate as
the analog interface. This means that when MCR.ADCCLKSEL = 1, the analog clock will not
shut down in IDLE mode.
23.4 Register descriptions
23.4.1 Introduction
Table 294 lists ADC registers with their address offsets and reset values.
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