FlexPWM RM0046
652/936 Doc ID 16912 Rev 5
Control 2 Register (CTRL2)
Figure 337. Control 2 Register (CTRL2)
Address:
Base + 0x0004 (Submodule 0)
Base + 0x0054 (Submodule 1)
Base + 0x00A4 (Submodule 2)
Base + 0x00F4 (Submodule 3) Access: User read/write
0123456789101112131415
R
DBGEN
WAITEN
INDEP
PWMA_INIT
PWMB_INIT
PWMX_INIT
INIT_SEL
FRCEN
0
FORCE_SEL
RELOAD_SEL
CLK_SEL
W
FORCE
Reset0000000000000000
Table 343. CTRL2 field descriptions
Field Description
0
DBGEN
Debug Enable
When this bit is set, the PWM will continue to run while the device is in debug mode. If the device
enters debug mode and this bit is cleared, then the PWM outputs are disabled until debug mode is
exited. At that point, the PWM pins resume operation as programmed in the PWM registers.
For certain types of motors (such as 3-phase AC), it is imperative that this bit be left in its default
state (in which the PWM is disabled in debug mode). Failure to do so could result in damage to the
motor or inverter. For other types of motors (such as DC motors), this bit might safely be set,
enabling the PWM in debug mode. The key point is that PWM parameter updates will not occur in
debug mode. Any motors requiring such updates should be disabled during debug mode. If in
doubt, leave this bit cleared.
1
WAITEN
WAIT Enable
When this bit is set, the PWM continues to run while the device is in WAIT/HALT mode. In this
mode, the peripheral clock continues to run, but the CPU clock does not. If the device enters
WAIT/HALT mode and this bit is cleared, then the PWM outputs are disabled until WAIT/HALT
mode is exited. At that point, the PWM pins resume operation as programmed in the PWM
registers.
For certain types of motors (such as 3-phase AC), it is imperative that this bit be left in its default
state (in which the PWM is disabled in WAIT/HALT mode). Failure to do so could result in damage
to the motor or inverter. For other types of motors (such as DC motors), this bit might safely be set,
enabling the PWM in WAIT/HALT mode. The key point is PWM parameter updates will not occur in
this mode. Any motors requiring such updates should be disabled during WAIT/HALT mode. If in
doubt, leave this bit cleared.
2
INDEP
Independent or Complementary Pair Operation
This bit determines whether the PWMA and PWMB channels will be independent PWMs or a
complementary PWM pair.
0 PWMA and PWMB form a complementary PWM pair.
1 PWMA and PWMB outputs are independent PWMs.
3
PWMA_INIT
PWMA Initial Value
This read/write bit determines the initial value for PWMA and the value to which it is forced when
FORCE_INIT is asserted.
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