ST SPC560P34 - Table 127. FEDR Field Descriptions; Figure 137. Flash ECC Data Register (FEDR); Figure 138. RAM ECC Address Register (REAR)

RM0046 Error Correction Status Module (ECSM)
Doc ID 16912 Rev 5 301/936
The data captured on a multi-bit non-correctable ECC error is undefined.
This register can only be read from the IPS programming model; any attempted write is
ignored.
RAM ECC Address Register (REAR)
The REAR is a 32-bit register for capturing the address of the last properly enabled ECC
event in the RAM memory. Depending on the state of the ECC Configuration Register, an
ECC event in the RAM causes the address, attributes and data associated with the access
to be loaded into the REAR, RESR, REMR, REAT and REDR registers, and the appropriate
flag (R1BC or RNCE) in the ECC Status Register to be asserted.
This register can only be read from the IPS programming model; any attempted write is
ignored.
Figure 137. Flash ECC Data register (FEDR)
Address: Base + 0x005C Access: User read-only
0123456789101112131415
R FEDR[31:16]
W
Reset:————————————————
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FEDR[15:0]
W
Reset:————————————————
Table 127. FEDR field descriptions
Name Description
0-31
FEDR[31:0]
Flash ECC Data Register
This 32-bit register contains the data associated with the faulting access of the last properly
enabled flash ECC event. The register contains the data value taken directly from the data bus.
Figure 138. RAM ECC Address register (REAR)
Address: Base + 0x0060 Access: User read-only
0123456789101112131415
R REAR[31:16]
W
Reset————————————————
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R REAR[15:0]
W
Reset————————————————