ST SPC560P34 User Manual

Enhanced Direct Memory Access (eDMA) RM0046
416/936 Doc ID 16912 Rev 5
Figure 198. Memory array terms
18.7.2 DMA programming errors
The eDMA performs various tests on the transfer control descriptor to verify consistency in
the descriptor data. Most programming errors are reported on a per channel basis with the
exception of two errors: group priority error and channel priority error, or EDMA_ESR[GPE]
and EDMA_ESR[CPE], respectively.
For all error types other than group or channel priority errors, the channel number causing
the error is recorded in the EDMA_ESR. If the error source is not removed before the next
activation of the problem channel, the error is detected and recorded again.
If priority levels are not unique, the highest (channel/group) priority that has an active
request is selected, but the lowest numbered (channel/group) with that priority is selected by
arbitration and executed by the eDMA engine. The hardware service request handshake
signals, error interrupts and error reporting are associated with the selected channel.
18.7.3 DMA request assignments
The assignments between the DMA requests from the modules to the channels of the
eDMA are shown in Table 1 97. The source column is written in C language syntax. The
syntax is module_instance.register[bit].
xADDR:
(Starting Address)
xSIZE:
(Size of one data
Minor Loop
(NBYTES in
Minor Loop, often
the same value
as xSIZE)
Offset (xOFF): Number of
bytes added to current
address after each transfer
(Often the same value
as xSIZE)
•
Minor Loop
Each DMA Source (S) and
Destination (D) has its own:
• Address (xADDR)
• Size (xSIZE)
• Offset (xOFF)
xLAST: Number of bytes
added to current address
Peripheral queues typically
have size and offset
equal to NBYTES
•
•
after Major Loop
(Typically used to
loop back)
transfer)
•
•
•
•
•
•
Last Minor Loop
• Modulo (xMOD)
• Last Address Adjustment
(xLAST) where x = S or D
•
•
•
Table 197. DMA request summary for eDMA
DMA Request Ch. Source Description
DMA_MUX_CHCONFIG0_SOURCE 0 DMA_MUX.CHCONFIG0[SOURCE] DMA MUX channel 0 source
DMA_MUX_CHCONFIG1_SOURCE 1 DMA_MUX.CHCONFIG1[SOURCE] DMA MUX channel 1 source
DMA_MUX_CHCONFIG2_SOURCE 2 DMA_MUX.CHCONFIG2[SOURCE] DMA MUX channel 2 source
DMA_MUX_CHCONFIG3_SOURCE 3 DMA_MUX.CHCONFIG3[SOURCE] DMA MUX channel 3 source
DMA_MUX_CHCONFIG4_SOURCE 4 DMA_MUX.CHCONFIG4[SOURCE] DMA MUX channel 4 source
DMA_MUX_CHCONFIG5_SOURCE 5 DMA_MUX.CHCONFIG5[SOURCE] DMA MUX channel 5 source

ST SPC560P34 Specifications

General

Brand	ST
Model	SPC560P34
Category	Microcontrollers
Language	English