ST SPC560P34 - Table 187. EDMA_CDSBR Field Descriptions; Table 188. EDMA_IRQRL Field Descriptions; Figure 189. Edma Interrupt Request Low Register (EDMA_IRQRL)

Enhanced Direct Memory Access (eDMA) RM0046
396/936 Doc ID 16912 Rev 5
eDMA Interrupt Request Register (EDMA_IRQRL)
The EDMA_IRQRL provide a bit map for the 16 channels signaling the presence of an
interrupt request for each channel. EDMA_IRQRL maps to channels 15–0.
The eDMA engine signals the occurrence of a programmed interrupt upon the completion of
a data transfer as defined in the transfer control descriptor by setting the appropriate bit in
this register. The outputs of this register are directly routed to the interrupt controller (INTC).
During the execution of the interrupt service routine associated with any given channel, it is
software’s responsibility to clear the appropriate bit, negating the interrupt request. Typically,
a write to the EDMA_CIRQR in the interrupt service routine is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this
register; it is also affected by writes to the EDMA_CIRQR. On writes to the EDMA_IRQRL, a
1 in any bit position clears the corresponding channel’s interrupt request. A zero in any bit
position has no affect on the corresponding channel’s current interrupt status. The
EDMA_CIRQR is provided so the interrupt request for a single channel can easily be
cleared without the need to perform a read-modify-write sequence to the EDMA_IRQRL.
Table 187. EDMA_CDSBR field descriptions
Field Description
0 Reserved.
1–7
CDSB[0:6]
Clear DONE status bit.
0–15 Clear the corresponding channel’s DONE bit
16–63 Reserved
64–127 Clear all TCD DONE bits
Bit 2 (CDSB1) is not used.
Figure 189. eDMA Interrupt Request Low Register (EDMA_IRQRL)
Address: Base + 0x0024 Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
INT
15
INT
14
INT
13
INT
12
INT
11
INT
10
INT
09
INT
08
INT
07
INT
06
INT
05
INT
04
INT
03
INT
02
INT
01
INT
00
W
Reset0000000000000000
Table 188. EDMA_IRQRL field descriptions
Field Description
16–31
INTn
eDMA interrupt request n.
0 The interrupt request for channel n is cleared.
1 The interrupt request for channel n is active.