ST SPC560P34 - Table 182. EDMA_SEEIR Field Descriptions; Table 183. EDMA_CEEIR Field Descriptions; Figure 184. Edma Set Enable Error Interrupt Register (EDMA_SEEIR)

RM0046 Enhanced Direct Memory Access (eDMA)
Doc ID 16912 Rev 5 393/936
eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
The EDMA_CEEIR provides a simple memory-mapped mechanism to clear a given bit in
the EDMA_EEIRL to disable the error interrupt for a given channel. The data value on a
register write causes the corresponding bit in the EDMA_EEIRL to be cleared. Setting bit 1
(CEEIn) provides a global clear function, forcing the entire contents of the EDMA_EEIRL to
be zeroed, disabling error interrupts for all channels. Reads of this register return all zeroes.
eDMA Clear Interrupt Request Register (EDMA_CIRQR)
The EDMA_CIRQR provides a simple memory-mapped mechanism to clear a given bit in
the EDMA_IRQRL to disable the interrupt request for a given channel. The given value on a
register write causes the corresponding bit in the EDMA_IRQRL to be cleared. Setting bit 1
(CINTn) provides a global clear function, forcing the entire contents of the EDMA_IRQRL to
be zeroed, disabling all DMA interrupt requests. Reads of this register return all zeroes.
Table 182. EDMA_SEEIR field descriptions
Field Description
0 Reserved.
1–7
SEEI[0:6]
Set enable error interrupt.
0–15 Set corresponding bit in EDMA_EIRRL
16–63 Reserved
64–127 Set all bits in EDMA_EEIRL
Bit 2 (SEEI1) is not used.
Figure 184. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
Address: Base + 0x001B Access: User write-only
01234567
R00000000
W
CEEI[0:6]
Reset00000000
Table 183. EDMA_CEEIR field descriptions
Field Description
0 Reserved.
1–7
CEEI[0:6]
Clear enable error interrupt.
0–15 Clear corresponding bit in EDMA_EEIRL
16–63 Reserved
64–127 Clear all bits in EDMA_EEIRL
Bit 2 (CEEI1) is not used.