ST SPC560P34 - Features

IEEE 1149.1 Test Access Port Controller (JTAGC) RM0046
842/936 Doc ID 16912 Rev 5
35.4 Features
The JTAGC is compliant with the IEEE 1149.1-2001 standard, and supports the following
features:
● IEEE 1149.1-2001 Test Access Port (TAP) interface
● Four pins (TDI, TMS, TCK, and TDO)—see Section 35.6, “External signal description.
● A 5-bit instruction register that supports several IEEE 1149.1-2001 defined instructions,
as well as several public and private MCU specific instructions.
● Test data registers: a bypass register, a boundary scan register, and a device
identification register.
● A TAP controller state machine that controls the operation of the data registers,
instruction register, and associated circuitry.
35.5 Modes of operation
The JTAGC uses a power-on reset indication as its primary reset signals. Several IEEE
1149.1-2001 defined test modes are supported, as well as a bypass mode.
35.5.1 Reset
The JTAGC is placed in reset when the TAP controller state machine is in the TEST-LOGIC-
RESET state. The TEST-LOGIC-RESET state is entered upon the assertion of the power-on
reset signal, or through TAP controller state machine transitions controlled by TMS.
Asserting power-on reset results in asynchronous entry into the reset state. While in reset,
the following actions occur:
● The TAP controller is forced into the test-logic-reset state, thereby disabling the test
logic and allowing normal operation of the on-chip system logic to continue unhindered.
● The instruction register is loaded with the IDCODE instruction.
In addition, execution of certain instructions can result in assertion of the internal system
reset. These instructions include EXTEST, CLAMP, and HIGHZ.
35.5.2 IEEE 1149.1-2001 defined test modes
The JTAGC supports several IEEE 1149.1-2001 defined test modes. The test mode is
selected by loading the appropriate instruction into the instruction register while the JTAGC
is enabled. Supported test instructions include EXTEST, HIGHZ, CLAMP, SAMPLE and
SAMPLE/PRELOAD. Each instruction defines the set of data registers that can operate and
interact with the on-chip system logic while the instruction is current. Only one test data
register path is enabled to shift data between TDI and TDO for each instruction.
The boundary scan register is enabled for serial access between TDI and TDO when the
EXTEST, SAMPLE or SAMPLE/PRELOAD instructions are active. The single-bit bypass
register shift stage is enabled for serial access between TDI and TDO when the HIGHZ,
CLAMP or reserved instructions are active. The functionality of each test mode is explained
in more detail in Section 35.8.4, “JTAGC instructions.