ST SPC560P34 - Figure 285. Main Configuration Register (MCR); Control Logic Registers

Analog-to-Digital Converter (ADC) RM0046
588/936 Doc ID 16912 Rev 5
23.4.2 Control logic registers
Main Configuration Register (MCR)
The Main Configuration Register (MCR) provides configuration settings for the ADC.
0x010C Channel 3 Data Register (CDR3) on page 23-601
0x0110 Channel 4 Data Register (CDR4) on page 23-601
0x0114 Channel 5 Data Register (CDR5) on page 23-601
0x0118 Channel 6 Data Register (CDR6) on page 23-601
0x011C Channel 7 Data Register (CDR7) on page 23-601
0x0120 Channel 8 Data Register (CDR8) on page 23-601
0x0124 Channel 9 Data Register (CDR9) on page 23-601
0x0128 Channel 10 Data Register (CDR10) on page 23-601
0x012C Channel 11 Data Register (CDR11) on page 23-601
0x0130 Channel 12 Data Register (CDR12) on page 23-601
0x0134 Channel 13 Data Register (CDR13) on page 23-601
0x0138 Channel 14 Data Register (CDR14) on page 23-601
0x013C Channel 15 Data Register (CDR15) on page 23-601
Table 294. ADC digital registers
Offset from base
address
0xFFE0_0000
Register name Location
Figure 285. Main Configuration Register (MCR)
Address: Base + 0x0000 Access: User read/write
0123456789101112131415
R
OWREN
WLSIDE
MODE
0000
NSTART
0
JTRGEN
JEDGE
JSTART
00
CTUEN
0
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000000
ADCLK
SEL
ABORT
CHAIN
ABORT
ACKO
0000
PWDN
W
Reset0000000000000001