ST SPC560P34 User Manual

eTimer RM0046
736/936 Doc ID 16912 Rev 5
26.9 Interrupts
Each of the channels within the eTimer can generate an interrupt from several sources. The
watchdog also generate interrupts. The interrupt service routine (ISR) must check the
related interrupt enables and interrupt flags to determine the actual cause of the interrupt.
26.10 DMA
Table 385. Interrupt summary
Core
Interrupt
Interrupt
Flag
Interrupt
Enable
Name Description
Channels
0–5
TCF TCFIE Compare interrupt Compare of counter and related compare register
TCF1 TCF1IE Compare 1 interrupt Compare of the counter and COMP1 register
TCF2 TCF2IE Compare 2 interrupt Compare of the counter and COMP2 register
TOF TOFIE Overflow interrupt Generated on counter roll-over or roll-under
IELF IELFIE Input Low Edge interrupt Falling edge of the secondary input signal
IEHF IEHFIE Input High Edge interrupt Rising edge of the secondary input signal
ICF1 ICF1IE Input Capture 1 interrupt Input capture event for CAPT1
ICF2 ICF2IE Input Capture 2 interrupt Input capture event for CAPT2
Watchdog WDF WDFIE
Watchdog time-out
interrupt
Watchdog has timed out
Redundant
Channel
Checking
RCF RCFIE
Redundant Channel
Fault interrupt
Miscompare with redundant channel
Table 386. DMA summary
DMA Request DMA Enable Name Description
Channels
0–5
ICF1DE CAPT1 read request CAPT1 contains a value
ICF2DE CAPT2 read request CAPT2 contains a value
CMPLD1DE CMPLD1 write request CMPLD1 needs an update
CMPLD2DE CMPLD2 write request CMPLD2 needs an update

ST SPC560P34 Specifications

General

Brand	ST
Model	SPC560P34
Category	Microcontrollers
Language	English