FlexPWM RM0046
700/936 Doc ID 16912 Rev 5
Figure 388. Full and half cycle reload frequency change
25.9.3 Reload flag
At every reload opportunity the PWM Reload Flag (RF) in the CTRL1 register is set. Setting
RF happens even if an actual reload is prevented by the LDOK bit. If the PWM reload
interrupt enable bit, RIE is set, the RF flag generates CPU interrupt requests allowing
software to calculate new PWM parameters in real time. When RIE is not set, reloads still
occur at the selected reload rate without generating CPU interrupt requests.
Figure 389. PWMF reload interrupt request
25.9.4 Reload errors
Whenever one of the VALx, or PSRC registers is updated, the RUF flag is set to indicate that
the data is not coherent. RUF will be cleared by a successful reload, which consists of the
reload signal while LDOK is set. If RUF is set and LDOK is clear when the reload signal
occurs, a reload error has taken place and the REF bit is set. If RUF is clear when a reload
signal asserts, then the data is coherent and no error will be flagged.
25.9.5 Initialization
Initialize all registers and set the LDOK bit before setting the RUN bit.
Note: Even if LDOK is not set, setting RUN also sets the RF flag. To prevent a CPU interrupt
request, clear the RIE bit before setting RUN.
Counter
Reload
Change
Reload
Frequency
Every two
opportunities
to every four
opportunities
to every
opportunity
to every two
opportunities
V
DD
CPU Interrupt Request
PWM Reload
DQ
CLK
CLR
Read RF as 1 then
Write 0 to RF
RESET
RF
RIE
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