Flash Memory RM0046
316/936 Doc ID 16912 Rev 5
Accesses are terminated under control of the appropriate read/write wait state control
setting. Thus, the access time of the operation is determined by the settings of the wait state
control fields. Access timing can be varied to account for the operating conditions of the
device (frequency, voltage, temperature) by appropriately setting the fields in the
programming model for either bank.
The platform Flash controller also has the capability of extending the normal AHB access
time by inserting additional wait states for reads and writes. This capability is provided to
allow emulation of other memories that have different access time characteristics. The
added wait state specifications are provided by bit 28 to bit 24 of Flash address
(haddr[28:24], see Table 1 40 and Table 1 4 1). These wait states are applied in addition to the
normal wait states incurred for Flash accesses. Refer to Section 17.2.17, “Wait state
emulation for more details.
Prefetching of next sequential page is blocked when haddr[28:24] is non-zero. Buffer hits are
also blocked as well, regardless of whether the access corresponds to valid data in one of
the page read buffers. These steps are taken to ensure that timing emulation is correct and
that excessive prefetching is avoided. In addition, to prevent erroneous operation in certain
rare cases, the buffers are invalidated on any non-sequential AHB access with a non-zero
value on haddr[28:24].
17.2.7 Access protections
The platform Flash controller provides programmable configurable access protections for
both read and write cycles from masters via the Platform Flash Access Protection Register
(PFAPR). It allows restriction of read and write requests on a per-master basis. This
functionality is described in Section , “Platform Flash Access Protection Register (PFAPR).
Detection of a protection violation results in an error response from the platform Flash
controller on the AHB transfer.
17.2.8 Read cycles — buffer miss
Read cycles from the Flash array are initiated by driving a valid access address on
bkn_fl_addr[23:0] and asserting bkn_fl_rd_en for the required setup (and hold) time before
(and after) the rising edge of hclk. The platform Flash controller then waits for the
programmed number of read wait states before sampling the read data on
bkn_fl_rdata[127:0]. This data is normally stored in the least-recently updated page read
buffer for bank0 in parallel with the requested data being forwarded to the AHB. For bank1,
the data is captured in the page-wide temporary holding register as the requested data is
forwarded to the AHB bus. Timing diagrams of basic read accesses from the Flash array are
shown in Figure 145 through Figure 148.
If the Flash access was the direct result of an AHB transaction, the page buffer is marked as
most-recently-used as it is being loaded. If the Flash access was the result of a speculative
prefetch to the next sequential line, it is first loaded into the least-recently-used buffer. The
status of this buffer is not changed to most-recently-used until a subsequent buffer hit
occurs.
17.2.9 Read cycles — buffer hit
Single cycle read responses to the AHB are possible with the platform Flash controller when
the requested read access was previously loaded into one of the bank0 page buffers. In
these “buffer hit” cases, read data is returned to the AHB data phase with a 0 wait state
response.
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