ST SPC560P34 User Manual

FlexPWM RM0046
672/936 Doc ID 16912 Rev 5
Fault Status Register (FSTS)
Table 358. FCTRL field descriptions
Field Description
0:3
FLVL
Fault Level
These read/write bits select the active logic level of the individual fault inputs. A reset clears FLVL.
0 A logic 0 on the fault input indicates a fault condition.
1 A logic 1 on the fault input indicates a fault condition.
4:7
FAUTO
Automatic Fault Clearing
These read/write bits select automatic or manual clearing of faults. A reset clears FAUTO.
0 Manual fault clearing. PWM outputs disabled by this fault are not enabled until the FFLAGx bit is
clear at the start of a half cycle. This is further controlled by the FSAFE bits.
1 Automatic fault clearing. PWM outputs disabled by this fault are enabled when the FFPINx bit is
clear at the start of a half cycle without regard to the state of FFLAGx bit.
8:11
FSAFE
Fault Safety Mode
These read/write bits select the safety mode during manual fault clearing. A reset clears FSAFE.
0 Normal mode. PWM outputs disabled by this fault are not enabled until the FFLAGx bit is clear at
the start of a half cycle without regard to the state of the FFPINx bit. The PWM outputs disabled
by this fault input will not be re-enabled until the actual FAULTx input signal de-asserts since the
fault input will combinationally disable the PWM outputs (as programmed in DISMAP).
1 Safe mode. PWM outputs disabled by this fault are not enabled until the FFLAGx bit is clear and
the FFPINx bit is clear at the start of a half cycle.
The FFPINx bit may indicate a fault condition still exists even though the actual fault signal at the FAULTx
pin is clear due to the fault filter latency.
12:15
FIE
Fault Interrupt Enables
This read/write bit enables CPU interrupt requests generated by the FAULTx pins. A reset clears
FIE.
0 FAULTx CPU interrupt requests disabled.
1 FAULTx CPU interrupt requests enabled.
The fault protection circuit is independent of the FIEx bit and is always active. If a fault is detected, the PWM
outputs are disabled according to the disable mapping register.
Figure 359. Fault Status Register (FSTS)
Address: Base + 0x014E Access: User read/write
0123456789101112131415
R000
FTEST
FFPIN 0 0
0
0
FFLAG
W
Reset0000001100000011

ST SPC560P34 Specifications

General

Brand	ST
Model	SPC560P34
Category	Microcontrollers
Language	English