Nexus Development Interface (NDI) RM0046
906/936 Doc ID 16912 Rev 5
Control State Register (CTL)
The Control State Register (CTL) is a 32-bit register that stores the value of certain internal
CPU state variables before the debug mode is entered. This register is affected by the
operations performed during the debug session and should normally be restored by the
external command controller when returning to normal mode. In addition to saved internal
state variables, two of the bits are used by emulation firmware to control the debug process.
In certain circumstances, emulation firmware must modify the content of this register as well
as the PC and IR values in the CPUSCR before exiting debug mode. These cases are
described below. Figure 520.
WAITING — Waiting State Status
This bit indicates whether the CPU was in the waiting state prior to entering debug mode. If
set, the CPU was in the waiting state. Upon exiting a debug session, the value of this bit in
the restored CPUSCR will determine whether the CPU re-enters the waiting state on a
go+exit.
0: CPU was not in the waiting state when debug mode was entered
1: CPU was in the waiting state when debug mode was entered
PCOFST — PC Offset Field
This field indicates whether the value in the PC portion of the CPUSCR must be adjusted
prior to exiting debug mode. Due to the pipelined nature of the CPU, the PC value must be
backed-up by emulation software in certain circumstances. The PCOFST field specifies the
value to be subtracted from the original value of the PC. This adjusted PC value should be
restored into the PC portion of the CPUSCR just prior to exiting debug mode with a go+exit.
In the event the PCOFST is non-zero, the IR should be loaded with a nop instruction instead
Figure 520. Control State Register (CTL)
0123456789101112131415
R
*
WAITING
W
Reset0001000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
PCOFST
PCINV
FFRA
IRSTAT0
IRSTAT1
IRSTAT2
IRSTAT3
IRSTAT4
IRSTAT5
IRSTAT6
IRSTAT7
IRSTAT8
IRSTAT9
W
Reset0000000000000000
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