RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 907/936
of the original IR value, otherwise the original value of IR should be restored. (But see
PCINV which overrides this field)
0000: No correction required.
0001: Subtract 0x04 from PC.
0010: Subtract 0x08 from PC.
0011: Subtract 0x0C from PC.
0100: Subtract 0x10 from PC.
0101: Subtract 0x14 from PC.
all other encodings are reserved
* — Internal State Bits
These control bits represent internal processor state and should be restored to their original
value after a debug session is completed, i.e when a e200z0h OnCE command is issued
with the GO and EX bits set and not ignored. When performing instruction execution during
a debug session (see Section , “e200z0h OnCE Debug Output (jd_debug_b)) which is not
part of the normal program execution flow, these bits should be set to a 0.
PCINV — PC and IR Invalid Status Bit
This status bit indicates that the values in the IR and PC portions of the CPUSCR are
invalid. Exiting debug mode with the saved values in the PC and IR will have unpredictable
results. Debug firmware should initialize the PC and IR values in the CPUSCR with desired
values prior to exiting debug mode if this bit was set when debug mode was initially entered.
0: No error condition exists.
1: Error condition exists. PC and IR are corrupted.
FFRA— Feed Forward RA Operand Bit
This control bit causes the content of the WBBR
low
to be used as the RA This control bit
causes the content of the WBBR
to be used as the RA operand value (RS for logical, mtspr,
mtdcr, cntlzw, and shift operations, RX for VLE se_ instructions, RT for e_{logical_op}2i type
instructions, and the value to use as the PC for calculating the LR update value for branch
with link type instructions) of the first instruction to be executed following an update of the
CPUSCR. This allows the debug firmware to update processor registers — initialize the
WBBR with the desired value, set the FFRA bit, and execute a ori Rx,Rx,0 instruction to the
desired register.
0: No action.
1: Content of WBBR
low
used as operand value
IRStat0 — IR Status Bit 0
This control bit indicates a TEA status for the IR.
0: No TEA occurred on the fetch of this instruction.
1: TEA occurred on the fetch of this instruction.
IRStat1 — IR Status Bit 1
This control bit indicates a TLB Miss status for the IR. (Note that this bit is reserved.)
0: No TLB Miss occurred on the fetch of this instruction.
1: TLB Miss occurred on the fetch of this instruction.
IRStat2 — IR Status Bit 2
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