Nexus Development Interface (NDI) RM0046
908/936 Doc ID 16912 Rev 5
This control bit indicates an Instruction Address Compare 1 event status for the IR.
0: No Instruction Address Compare 1 event occurred on the fetch of this instruction.
1: An Instruction Address Compare 1 event occurred on the fetch of this instruction.
IRStat3 — IR Status Bit 3
This control bit indicates an Instruction Address Compare 2 event status for the IR.
0: No Instruction Address Compare 2 event occurred on the fetch of this instruction.
1: An Instruction Address Compare 2 event occurred on the fetch of this instruction.
IRStat4 — IR Status Bit 4
This control bit indicates an Instruction Address Compare 3 event status for the IR.
0: No Instruction Address Compare 3 event occurred on the fetch of this instruction.
1: An Instruction Address Compare 3 event occurred on the fetch of this instruction.
IRStat5 — IR Status Bit 5
This control bit indicates an Instruction Address Compare 4 event status for the IR.
0: No Instruction Address Compare 4 event occurred on the fetch of this instruction.
1: An Instruction Address Compare 4 event occurred on the fetch of this instruction.
IRStat6 — IR Status Bit 6
This control bit indicates a Parity Error status for the IR. (Note that this bit is reserved.)
0: No Parity Error occurred on the fetch of this instruction.
1: Parity Error occurred on the fetch of this instruction.
IRStat7 — IR Status Bit 7
This control bit indicates a Precise External Termination Error status for the IR.
0: No Precise External Termination Error occurred on the fetch of this instruction.
1: Precise External Termination Error occurred on the fetch of this instruction.
IRStat8 — IR Status Bit 8
This control bit indicates the Power Architecture technology VLE status for the IR. (Note that
this bit is always set on Z0Hn2p.)
0: IR contains a BookE instruction.
1: IR contains a Power Architecture technology VLE instruction, aligned in the Most
Significant Portion of IR if 16-bit.
IRStat9 — IR Status Bit 9
This control bit indicates the Power Architecture technology VLE Byte-ordering Error status
for the IR, or a BookE misaligned instruction fetch, depending on the state of IRStat8. (Note
that this bit is reserved on Z0Hn2p.)
0: IR contains an instruction without a byte-ordering error and no Misaligned Instruction
Fetch Exception has occurred (no MIF).
1: If IRStat8 = ‘0’, A BookE Misaligned Instruction Fetch Exception has occurred while
filling the IR.
If IRStat8 = ‘1’, IR contains an instruction with a byte-ordering error due to mismatched
VLE page attributes, or due to E indicating little-endian for a VLE page.
Emulation firmware should modify the content of the CTL, PC, and IR values in the
CPUSCR during execution of debug related instructions as well as just prior to exiting debug
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