RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 909/936
with a go+exit command. During the debug session, the CTL register should be written with
the FFRA bit set as appropriate, and all other bits set to ‘0’, and the IR set to the value of the
desired instruction to be executed. IRStat8 will be used to determine the type of instruction
present in the IR.
Just prior to exiting debug mode with a go+exit, the PCINV status bit which was originally
present when debug mode was first entered should be tested, and if set, the PC and IR
initialized for performing whatever recovery sequence is appropriate for a faulted exception
vector fetch. If the PCINV bit is cleared, then the PCOFST bits should be examined to
determine whether the PC value must be adjusted. Due to the pipelined nature of the CPU,
the PC value must be backed-up by emulation software in certain circumstances. The
PCOFST field specifies the value to be subtracted from the original value of the PC. This
adjusted PC value should be restored in to the PC portion of the CPUSCR just prior to
exiting debug mode with a go+exit. In the event the PCOFST is non-zero, the IR should be
loaded with a nop instruction (such as ori r0,r0,0) instead of the original IR value, otherwise
the original value of IR should be restored. Note that when a correction is made to the PC
value, it will generally point to the last completed instruction, although that instruction will not
be re-executed. The nop instruction is executed instead, and instruction fetch and execution
will resume at location PC+4. IRStat8 will be used to determine the type of instruction
present in the IR, thus should be cleared in this case. Note that debug events which may
occur on the nop (ICMP) will be generated (and optionally counted) if enabled.
For the CTL register, the internal state bits should be restored to their original value. The
IRStatus bits should be set to ‘0’s if the PC was adjusted. If no PC adjustment was
performed, emulation firmware should determine whether IRStat2-5 should be set to ‘0’ to
avoid re-entry into debug mode for an instruction breakpoint request. Upon exiting debug
mode with go+exit, if one of these bits is set, debug mode will be re-entered prior to any
further instruction execution.
Program Counter Register (PC)
The PC is a 32-bit register that stores the value of the program counter which was present
when the chip entered the debug mode. It is affected by the operations performed during the
debug mode and must be restored by the external command controller when the CPU
returns to normal mode. PC normally points to the instruction contained in the IR portion of
CPUSCR. If debug firmware wishes to redirect program flow to an arbitrary location, the PC
and IR should be initialized to correspond to the first instruction to be executed upon
resumption of normal processing. Alternatively, the IR may be set to a nop and the PC set to
point to the location prior to the location at which it is desired to redirect flow to. On exiting
debug mode, the nop will be executed, and instruction fetch and execution will resume at
PC+4.
Write-Back Bus Register (WBBR
low
, WBBR
high
)
WBBR is used as a means of passing operand information between the CPU and the
external command controller. Whenever the external command controller needs to read the
contents of a register or memory location, it will force the chip to execute an instruction that
brings that information to WBBR. WBBR
low
holds the 32-bit result of most instructions
including load data returned for a load or load with update instruction. WBBR
high
holds the
updated effective address calculated by a load with update instruction. It is undefined for
other instructions.
As an example, to read the lower 32 bits of processor register r1, an e_ori r1,r1,0 instruction
is executed, and the result value of the instruction will be latched into WBBR
low
. The
contents of WBBR
low
can then be delivered serially to the external command controller. To
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