RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 863/936
IAC compares perform a 31-bit compare for VLE instructions. Each halfword fetched by the
instruction fetch unit will be marked with a set of bits indicating whether an Instruction
Address Compare occurred on that halfword. Debug exceptions will occur if enabled and a
16-bit instruction, or the first halfword of a 32-bit instruction, is tagged with an IAC hit.
36.10.2 Data Address Compare Event
Data Address Compare debug events occur when enabled and execution of a load or store
class instruction results in a data access that meets the criteria specified in the DBCR0,
DBCR2, DBCR4, DAC1, DAC2, DVC1, and DVC2 Registers. Data address compares may
specify user/supervisor mode and data space (MSR
DS
), along with an effective address,
masked effective address, or range of effective addresses for comparison. This event can
occur and be recorded in DBSR regardless of the setting of MSR
DE
. Two address compare
values (DAC1, DAC2) are provided.
Note: In contrast to the Power Architecture technology, Data Address Compare events on
e200z0h do not prevent the load or store class instruction from completing. If a load or store
class instruction completes successfully without a Data TLB or Data Storage interrupt, Data
Address Compare exceptions are reported at the completion of the instruction. If the
exception results in a precise Debug interrupt, the address value saved in DSRR0 (or
CSRR0 if the Debug APU is disabled) is the address of the instruction following the load or
store class instruction. For DVC DAC events, the exception can be imprecisely reported
even further past the load or store class instruction generating the event (without
necessarily affecting DBSR
IDE
) and the saved address value can point to a subsequent
instruction past the next instruction. This occurrence is indicated in the DBSR
DAC_OFST
field.
If a load or store class instruction does not complete successfully due to a Data Storage
exception, and a Data Address Compare debug exception also occurs, the result is an
imprecise Debug interrupt, the address value saved in DSRR0 (or CSRR0 if the Debug APU
is disabled) is the address of the load or store class instruction, and the DBSR
IDE
bit will be
set. In addition to occurring when DBCR0
IDM
=1, this circumstance can also occur when
DBCR0
EDM
=1.
Note: DAC events will not be recorded or counted if a lmw or stmw instruction is interrupted prior
to completion by a critical input or external input interrupt.
Note: DAC events are not signaled on the second portion of a misaligned load or store that is
broken up into two separate accesses.
Note: DAC[1,2] events are not signaled if DVC[1,2]M is non-zero and a DSI or DTLB exception
occurs on the load or store, since the load or store access is not performed. For a lmw or
stmw transfer however, if a DVC successfully occurs on a transfer and a later transfer
encounters a DSI or DTLB exception, the DAC event will be reported, since a successful
data value compare took place
(1)
.
Data Address Compare Event Status Updates
Data Address Compare debug events with Data Value compares can be reported
ambiguously in several circumstances involving back-to-back load or store class
instructions. If the first load or store class instruction generates a DVC DAC, a second load
or store class instruction may also generate a DAC or DVC DAC event, or may generate A
DTLB or DSI exception with or without a simultaneous DAC event. Ta bl e 4 59 outlines the
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