FlexPWM RM0046
664/936 Doc ID 16912 Rev 5
Fault Disable Mapping register (DISMAP)
This register determines which PWM pins are disabled by the fault protection inputs,
illustrated in Table 3 5 0 in Section 25.8.12, “Fault protection. Reset sets all of the bits in the
fault disable mapping register.
Deadtime Count registers (DTCNT0, DTCNT1)
Deadtime operation is only applicable to complementary channel operation. Reset sets the
deadtime count registers to a default value of 0x07FF, selecting a deadtime of 4095
peripheral clock cycles. These registers are not byte accessible.
Figure 350. Fault Disable Mapping register (DISMAP)
Address:
Base + 0x0022 (Submodule 0)
Base + 0x0072 (Submodule 1)
Base + 0x00C2 (Submodule 2)
Base + 0x0112 (Submodule 3) Access: User read/write
0123456789101112131415
R1111
DISX[3:0] DISB[3:0] DISA[3:0]
W
Reset1111111111111111
Table 352. DISMAP field descriptions
Field Description
4:7
DISX
PWMX Fault Disable Mask
Each of the 4 bits of this read/write field is one-to-one associated with the four FAULTx inputs. The
PWMX output will be turned off if there is a logic 1 on a FAULTx input and a 1 in the corresponding bit of
the DISX field. A reset sets all DISX bits.
Note: DISX[3:2] not used on SPC560P40/34.
8:11
DISB
PWMB Fault Disable Mask
Each of the 4 bits of this read/write field is one-to-one associated with the four FAULTx inputs. The
PWMB output will be turned off if there is a logic 1 on a FAULTx input and a 1 in the corresponding bit of
the DISB field. A reset sets all DISB bits.
Note: DISB[3:2] not used on SPC560P40/34.
12:15
DISA
PWMA Fault Disable Mask
Each of the 4 bits of this read/write field is one-to-one associated with the four FAULTx inputs. The
PWMA output will be turned off if there is a logic 1 on a FAULTx input and a 1 in the corresponding bit of
the DISA field. A reset sets all DISA bits.
Note: DISA[3:2] not used on SPC560P40/34.
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