Peripheral Bridge (PBRIDGE) RM0046
280/936 Doc ID 16912 Rev 5
13.2 Functional description
The PBRIDGE serves as an interface between a system bus and the peripheral (slave) bus.
It functions as a protocol translator. Accesses that fall within the address space of the
PBRIDGE are decoded to provide individual module selects for peripheral devices on the
slave bus interface.
13.2.1 Access support
Aligned 32-bit word accesses, halfword accesses, and byte accesses are supported for the
peripherals. Peripheral registers must not be misaligned, although no explicit checking is
performed by the PBRIDGE.
Note: Data accesses that cross a 32-bit boundary are not supported.
Peripheral Write Buffering
Buffered writes are not supported by the device PBRIDGE.
Read cycles
Two-clock read accesses are possible with the Peripheral Bridge when the requested
access size is 32-bits or smaller, and is not misaligned across a 32-bit boundary.
Write cycles
Three clock write accesses are possible with the Peripheral Bridge when the requested
access size is 32-bits or smaller. Misaligned writes that cross a 32-bit boundary are not
supported.
13.2.2 General operation
Slave peripherals are modules that contain readable/writable control and status registers.
The system bus master reads and writes these registers through the PBRIDGE. The
PBRIDGE generates module enables, the module address, transfer attributes, byte enables,
and write data as inputs to the slave peripherals. The PBRIDGE captures read data from the
slave interface and drives it on the system bus.
The PBRIDGE occupies a 64 MB portion of the address space. The register maps of the
slave peripherals are located on 16-KB boundaries. Each slave peripheral is allocated one
16-KB block of the memory map, and is activated by one of the module enables from the
PBRIDGE.
The PBRIDGE is responsible for indicating to slave peripherals if an access is in supervisor
or user mode. All eDMA transfers are done in supervisor mode.
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