ST SPC560P34 - Figure 423. Change Lock Settings for 16-Bit Protected Addresses; Figure 424. Change Lock Settings for 32-Bit Protected Addresses

RM0046 Functional Safety
Doc ID 16912 Rev 5 743/936
Figure 422 showed four registers that can be protected 8-bit wise. In Figure 423 registers
with 16-bit protection and in Figure 424 registers with 32-bit protection are shown.
Figure 423. Change lock settings for 16-bit protected addresses
On the right side of Figure 423 it is shown that the data written to SLBRn[SLB0] is
automatically written to SLBRn[SLB1] also. This is done as the address reflected by
SLBRn[SLB0] is protected 16-bit wise. Note that in this case the write enable SLBRn[WE0]
must be set while SLBRn[WE1] does not matter. As the enable bits SLBRn[WE[3:2]] are
cleared the lock bits SLBRn[SLB[3:2]] remain unchanged.
In the example on the left side of Figure 423 the data written to SLBRn[SLB0] is mirrored to
SLBRn[SLB1] and the data written to SLBRn[SLB2] is mirrored to SLBRn[SLB3] as for both
registers the write enables are set.
In Figure 424 a 32-bit wise protected register is shown. When SLBRn[WE0] is set the data
written to SLBRn[SLB0] is automatically written to SLBRn[SLB[3:1]] also. Otherwise
SLBRn[SLB[3:0]] remains unchanged.
Figure 424. Change lock settings for 32-bit protected addresses
Figure 425 shows an example that has a mixed protection size configuration.
SLB0 SLB1 SLB2 SLB3
SLBR
update lock bits
1SLBRn[WE[3:0]]
to SLB0
write data
to SLB1 to SLB2 to SLB3
X1X
SLB0 SLB1 SLB2 SLB3
SLBR
update lock bits
1SLBRn[WE[3:0]]
to SLB0
write data
to SLB1 to SLB2 to SLB3
X00
1
SLB0 SLB1 SLB2 SLB3
SLBRn[WE[3:0]]
SLBR[SLB[3:0]]
update lock bits
to SLB0
write data
to SLB1 to SLB2 to SLB3
XXX