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Nexus Development Interface (NDI) RM0046

890/936 Doc ID 16912 Rev 5

Figure 514. IEEE 1149.1-2001 TAP Controller State Machine

Access to processor registers and the contents of memory locations are performed by

enabling external debug mode (setting DBCR0

EDM

to ‘1’), placing the processor into debug

mode, followed by scanning instructions and data into and out of the CPU Scan Chain

(CPUSCR); execution of scanned instructions by the CPU is used as the method to access

required data. Memory locations may be read by scanning a load instruction into the

e200z0h core which will reference the desired memory location, executing the load

instruction, and then scanning out the result of the load. Other resources are accessed in a

similar manner.

The initial entry by the CPU into the debug state (or mode) from normal, waiting, stopped,

halted, or checkstop states (all indicated via the OnCE Status Register (OSR), Section ,

“e200z0h OnCE Status Register) by assertion of one or more debug requests, begins a

debug session. The jd_debug_b output signal indicates that a debug session is in progress,

and the OSR will indicate the CPU is in the debug state. Instructions may the be single-

stepped by scanning new values into the CPUSCR, and performing a OnCE go+noexit

Capture - DR

Shift - DR

Exit1 - DR

Pause - DR

Exit2 - DR

Update - DR

Select - IR

Scan

Capture - IR

Shift - IR

Exit1 - IR

Pause - IR

Exit2 - IR

Update - IR

Select DR-

Scan

Run - Test /

Idle

Test-Logic-

Reset

NOTE: The value shown adjacent to each state transition in this figure represents the value of TMS

at the time of a rising edge of TCK.

ST SPC560P34 User Manual

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