RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 903/936
36.12.7 Methods of Entering Debug Mode
The OnCE Status Register indicates that the CPU has entered the debug mode via the
DEBUG status bit. The following sections describe how e200z0h Debug Mode is entered
assuming the OnCE circuitry has been enabled. e200z0h OnCE operation is enabled by the
assertion of the jd_en_once input (see Section ).
External Debug Request During RESET
Holding the jd_de_b signal asserted during the assertion of p_reset_b, and continuing to
hold it asserted following the negation of p_reset_b causes the e200z0h core to enter
Debug Mode. After receiving an acknowledge via the OnCE Status Register DEBUG bit, the
external command controller should negate the jd_de_b signal before sending the first
command. Note that in this case the e200z0h core does not execute an instruction before
entering Debug Mode, although the first instruction to be executed may be fetched prior to
entering Debug Mode.
In this case, all values in the debug scan chain will be undefined, and the external Debug
Control Module is responsible for proper initialization of the chain before debug mode is
exited. In particular, the exception processing associated with reset, may not be performed
when the debug mode is exited, thus, the Debug controller must initialize the PC, MSR, and
IR to the image that the processor would have obtained in performing reset exception
processing, or must cause the appropriate reset to be re-asserted.
Debug Request During RESET
Asserting a debug request by setting the DR bit in the OCR during the assertion of
p_reset_b causes the chip to enter debug mode. In this case the chip may fetch the first
instruction of the reset exception handler, but does not execute an instruction before
entering debug mode. In this case, all values in the debug scan chain will be undefined, and
the external Debug Control Module is responsible for proper initialization of the chain before
debug mode is exited. In particular, the exception processing associated with reset may not
be performed when the debug mode is exited, thus, the Debug controller must initialize the
PC, MSR, and IR to the image that the processor would have obtained in performing reset
exception processing, or must cause the appropriate reset to be re-asserted.
Debug Request During Normal Activity
Asserting a debug request by setting the DR bit in the OCR during normal chip activity
causes the chip to finish the execution of the current instruction and then enter the debug
mode. Note that in this case the chip completes the execution of the current instruction and
stops after the newly fetched instruction enters the CPU instruction register. This process is
the same for any newly fetched instruction including instructions fetched by the interrupt
processing, or those that will be aborted by the interrupt processing.
Debug Request During Waiting, Halted or Stopped State
Asserting a debug request by setting the DR bit in the OCR when the chip is in the Waiting
state (p_waiting asserted), Halted state (p_halted asserted) or Stopped state (p_stopped
asserted) causes the CPU to exit the state and enter the debug mode once the CPU clock
m_clk has been restored. Note that in this case, the CPU will negate the p_waiting,
p_halted and p_stopped outputs. Once the debug session has ended, the CPU will return
to the state it was in prior to entering debug mode.
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