Nexus Development Interface (NDI) RM0046
884/936 Doc ID 16912 Rev 5
Table 463 provides bit definitions for the Debug External Resource Control Register. Note
that DBERC0 controls are disabled when DBCR0
EDM
=0.
Table 464. DBERC0 Bit Definitions
Bit(s) Name Description
0—Reserved
1IDM
Internal Debug Mode control
0 – Internal Debug mode may not be enabled by software. DBCR0
IDM
is owned exclusively
by hardware. mtspr DBCR0–4, and DBSR is always ignored. No resource sharing occurs,
regardless of the settings of other fields in DBERC0. Hardware exclusively owns all
resources.
1 – Internal Debug mode may be enabled by software. DBCR0
IDM
owned by software.
DBCR0
IDM
software readable/writeable.
When DBERC0
IDM
=1, writes to hardware-owned bits in DBCR0–4, and DBSR via mtspr are
ignored.
2RST
Reset Field Control
0 – DBCR0
RST
owned exclusively by hardware debug. No mtspr access by software to
DBCR0
RST
field.
1 – DBCR0
RST
accessible by software debug. DBCR0
RST
is software readable/writeable.
3 UDE
Unconditional Debug Event
0 – Event owned by hardware debug. No mtspr access by software to DBSR
UDE
field.
1 – Event owned by software debug. DBSR
UDE
is software readable/writeable.
4ICMP
Instruction Complete Debug Event
0 – Event owned by hardware debug. No mtspr access by software to DBCR0
ICMP
or
DBSR
ICMP
fields.
1 – Event owned by software debug. DBCR0
ICMP
and DBSR
ICMP
are software
readable/writeable.
5BRT
Branch Taken Debug Event
0 – Event owned by hardware debug. No mtspr access by software to DBCR0
BRT
or
DBSR
BRT
fields.
1 – Event owned by software debug. DBCR0
BRT
and DBSR
BRT
are software
readable/writeable.
6IRPT
Interrupt Taken Debug Event
0 – Event owned by hardware debug. No mtspr access by software to DBCR0
IRPT
or
DBSR
IRPT
fields.
1 – Event owned by software debug. DBCR0
IRPT
and DBSR
IRPT
are software
readable/writeable.
7TRAP
Trap Taken Debug Event
0 – Event owned by hardware debug. No mtspr access by software to DBCR0
TRAP
or
DBSR
TRAP
fields.
1 – Event owned by software debug. DBCR0
TRAP
and DBSR
TRAP
are software
readable/writeable.
8IAC1
Instruction Address Compare 1 Debug Event
0 – Event owned by hardware debug. No mtspr access by software to IAC1 control and status
fields.
1 – Event owned by software debug. DBCR0
IAC1
and DBSR
IAC1
are software
readable/writeable.
To Next Page
Loading...
