ST SPC560P34 - Table 401. FCU_MCR Field Description

RM0046 Fault Collection Unit (FCU)
Doc ID 16912 Rev 5 761/936
Fault Flag Register (FCU_FFR)
The FCU_FFR contains the latched fault indication coming from the device. The FCU reacts
on faults only if the respective enable bit for a fault is set in the Fault Enable Register
(FCU_FER). In this case, the Alarm or Fault state is entered, depending on the user’s
selection. To enter Alarm state, the bit for the fault has to be set in the Timeout Enable
Register (FCU_TER), otherwise Fault state is entered and output pins are communicating
the internal fault.
No faults are latched in Init state (refer to state machine Figure 449).
The FCU_FFR is copied into Frozen Fault Flag Register (FCU_FFFR) only when the FCU
goes into Fault state.
Each single flag can be cleared:
● In hardware, if the flag disappears due to hardware intervention. Bits 16:31 of the
FCU_FFR store hardware-recoverable flags.
● In software, if the user application can recover from a faulty situation. Bits 0:4 of the
FCU_FFR store software-recoverable flags.
Table 401. FCU_MCR field description
Field Description
0
MCL
Module Configuration Lock
0: Configuration not locked, FCU remains in Init state
1: Configuration locked, FCU moves to Normal state
1-2
TM[1:0]
Test Mode
00: Test Mode not entered
01: Test Mode entered (fake faults can be generated), output pins disabled
10: Test Mode entered (fake faults can be generated), output pins enabled
11: Test Mode not entered
22-23
PS[1:0]
Polarity select
00: FCU[0] has normal polarity, FCU[1] has normal polarity.
01: FCU[0] has inverted polarity, FCU[1] has normal polarity.
10: FCU[0] has normal polarity, FCU[1] has inverted polarity.
11: FCU[0] has inverted polarity, FCU[1] has inverted polarity.
24-25
FOM[1:0]
Fault output mode selection
00: Dual-Rail (default state)
01: Time Switching
10: Bi-Stable
11: Reserved
26-31
FOP[5:0]
Fault Output Prescaler
000000: Input clock frequency is divided by [4096 × (0 + 1) × 2], where 4096 is a fixed prescaler.
000001: Input clock frequency is divided by [4096 × (1 + 1) × 2], where 4096 is a fixed prescaler.
000010: Input clock frequency is divided by [4096 × (2 + 1) × 2], where 4096 is a fixed prescaler.
000011: Input clock frequency is divided by [4096 × (3 + 1) × 2], where 4096 is a fixed prescaler.
000100: Input clock frequency is divided by [4096 × (4 + 1) × 2], where 4096 is a fixed prescaler.
...
Default at reset is 0x07 (input clock frequency is divided by [4096 × (7 + 1) × 2]).