ST SPC560P34 - Figure 506. DVC1, DVC2 Registers; Debug Control and Status Registers

RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 869/936
participate in the comparison, they are implicitly masked. Software must also program the
DVC1(2) register byte positions based on the endian mode and alignment of the access.
Misaligned accesses are not fully supported, since the data address and data value
comparisons are only performed on the initial access in the case of a misaligned access;
thus, accesses which cross a 32-bit boundary cannot be fully matched. For address and
size combinations which involve two transfers, only the initial transfer is used for data
address and value matching. DVC1 and DVC2 may be read or written using mtspr and
mfspr instructions.
36.11.2 Debug Control and Status Registers
Debug Control Registers (DBCR0, DBCR1, DBCR2, DBCR4, and DBERC0) are used to
enable debug events, reset the processor, and set the debug mode of the processor. The
Debug Status register (DBSR) records debug exceptions while Internal or External Debug
Mode is enabled.
e200z0h requires that a context synchronizing instruction follow a
mtspr DBCR0-4 or
DBSR to ensure that any alterations enabling/disabling debug events are effective. The
context synchronizing instruction may or may not be affected by the alteration. Typically, an
isync instruction is used to create a synchronization boundary beyond which it can be
guaranteed that the newly written control values are in effect.
For watchpoint generation, configuration settings contained in DBCR1and DBCR2 are used,
even though the corresponding event(s) may be disabled (via DBCR0) from setting DBSR
flags.
Debug Control Register 0 (DBCR0)
Debug Control Register 0 is used to enable debug modes and controls which debug events
are allowed to set DBSR flags. e200z0h adds some implementation specific bits to this
register, as seen in Figure 507
Figure 506. DVC1, DVC2 Registers
SPR - 318 (DVC1), 319 (DVC2);
0123456789101112131415
R
B0 B1
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
B2 B3
W
Reset0000000000000000