ST SPC560P34 - Table 48. Run Peripheral Configuration Registers (ME_RUN_PC0; Table 48. Run Peripheral Configuration Registers (ME_RUN_PC0...7) Field Descriptions

Mode Entry Module (MC_ME) RM0046
166/936 Doc ID 16912 Rev 5
Run Peripheral Configuration Registers (ME_RUN_PC0…7)
These registers configure eight different types of peripheral behavior during run modes.
Figure 60. Run Peripheral Configuration Registers (ME_RUN_PC0…7)
Address 0xC3FD_C080 - 0xC3FD_C09C Access: User read, Supervisor read/write, Test read/write
0123456789101112131415
R0000000000000000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R00000000
RUN3 RUN2 RUN1 RUN0
DRUN
SAFE
TEST
RESET
W
Reset0000000000000000
Table 48. Run Peripheral Configuration Registers (ME_RUN_PC0…7) Field Descriptions
Field Description
RUN3
Peripheral control during RUN3
0 Peripheral is frozen with clock gated
1 Peripheral is active
RUN2
Peripheral control during RUN2
0 Peripheral is frozen with clock gated
1 Peripheral is active
RUN1
Peripheral control during RUN1
0 Peripheral is frozen with clock gated
1 Peripheral is active
RUN0
Peripheral control during RUN0
0 Peripheral is frozen with clock gated
1 Peripheral is active
DRUN
Peripheral control during DRUN
0 Peripheral is frozen with clock gated
1 Peripheral is active
SAFE
Peripheral control during SAFE
0 Peripheral is frozen with clock gated
1 Peripheral is active
TEST
Peripheral control during TEST
0 Peripheral is frozen with clock gated
1 Peripheral is active
RESET
Peripheral control during RESET
0 Peripheral is frozen with clock gated
1 Peripheral is active