RM0046 System Integration Unit Lite (SIUL)
Doc ID 16912 Rev 5 255/936
Interrupt Status Flag Register (ISR)
This register holds the interrupt flags.
Interrupt Request Enable Register (IRER)
This register enables the interrupt messaging to the interrupt controller.
Figure 100. Interrupt Status Flag Register (ISR)
Address:
Base + 0x0014 Access: User read/write
0123456789101112131415
R EIF[24:16]
W
w1c
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R EIF[15:0]
Ww1c
Reset0000000000000000
Table 93. ISR field descriptions
Field Description
EIFn
External Interrupt Status Flag n
This flag can be cleared only by writing a 1. Writing a 0 has no effect. If enabled (IRERn), EIFn
causes an interrupt request.
0: No interrupt event has occurred on the pad.
1: An interrupt event as defined by IREERn and IFEERn has occurred.
Figure 101. Interrupt Request Enable Register (IRER)
Address:
Base + 0x0018 Access: User read/write
0123456789101112131415
R
IRE[24:16]
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
IRE[15:0]
W
Reset0000000000000000
Table 94. IRER field descriptions
Field Description
IREn
External Interrupt Request Enable n
0: Interrupt requests from the corresponding EIFn bit are disabled.
1: A set EIFn bit causes an interrupt request.
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