Error Correction Status Module (ECSM) RM0046
290/936 Doc ID 16912 Rev 5
IPS Module Configuration (IMC) register
The IMC is a 32-bit read-only register identifying the presence/absence of the 32 low-order
IPS peripheral modules connected to the primary slave bus controller. The state of this
register is defined by a module input signal; it can only be read from the IPS programming
model. Any attempted write is ignored.
Miscellaneous Reset Status Register (MRSR)
The MRSR contains a bit for each of the reset sources to the device. An asserted bit
indicates the last type of reset that occurred. Only one bit is set at any time in the MRSR,
reflecting the cause of the most recent reset as signaled by device reset input signals. The
MRSR can only be read from the IPS programming model. Any attempted write is ignored.
Table 116. ASC field descriptions
Field Description
DP64
64-bit Datapath
0 Datapath width is 32 bits.
1 Datapath width is 64 bits.
ASC[7:0]
XBAR Slave Configuration
0 Bus slave connection to XBAR output port n is not present.
1 Bus slave connection to XBAR output port n is present.
Figure 127. IPS Module Configuration (IMC) register
Address Base + 0x0008 Access: User read-only
0123456789101112131415
R MC[31:16]
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
RMC[15:0]
W
Reset1110000000000000
Table 117. IMC field descriptions
Field Description
0-31
MC[31:0]
IPS Module Configuration
0 IPS module connection to decoded slot n not present
1 IPS module connection to decoded slot n present
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