ST SPC560P34 - Figure 81. INTC End-Of-Interrupt Register (INTC_EOIR); Figure 82. INTC Software Set;Clear Interrupt Register 0-3 (INTC_SSCIR[0:3])

Interrupt Controller (INTC) RM0046
216/936 Doc ID 16912 Rev 5
INTC End-of-Interrupt Register (INTC_EOIR)
Writing to the end-of-interrupt register signals the end of the servicing of the interrupt
request. When the INTC_EOIR is written, the priority last pushed on the LIFO is popped into
INTC_CPR. An exception to this behavior is described in Section , “Hardware vector mode.
The values and size of data written to the INTC_EOIR are ignored. The values and sizes
written to this register neither update the INTC_EOIR contents or affect whether the LIFO
pops. For possible future compatibility, write four bytes of all 0s to the INTC_EOIR.
Reading the INTC_EOIR has no effect on the LIFO.
INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0_3–
INTC_SSCIR4_7)
Figure 81. INTC End-of-Interrupt Register (INTC_EOIR)
Address Base + 0x0018 Access: Write-only
0123456789101112131415
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset0000000000000000
Figure 82. INTC Software Set/Clear Interrupt Register 0–3 (INTC_SSCIR[0:3])
Address Base + 0x0020 Access: User read/write
0123456789101112131415
R 0 0 0 0 0 0 0
CLR
0
0 0 0 0 0 0 0
CLR
1
W SET0 SET1
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0
CLR
2
0 0 0 0 0 0 0
CLR
3
W
SET2 SET3
Reset0000000000000000