RM0046 Reset Generation Module (MC_RGM)
Doc ID 16912 Rev 5 189/936
8.1.2 Features
The MC_RGM contains the functionality for the following features:
● ‘destructive’ resets management
● ‘functional’ resets management
● signalling of reset events after each reset sequence (reset status flags)
● conversion of reset events to SAFE mode or interrupt request events
● short reset sequence configuration
● bidirectional reset behavior configuration
● boot mode capture on RESET_B deassertion
8.1.3 Reset Sources
The different reset sources are organized into two families: ‘destructive’ and ‘functional’.
● A ‘destructive’ reset source is associated with an event related to a critical - usually
hardware - error or dysfunction. When a ‘destructive’ reset event occurs, the full reset
sequence is applied to the device starting from PHASE0. This resets the full device
ensuring a safe start-up state for both digital and analog modules. ‘Destructive’ resets
are
– power-on reset
– 1.2V low-voltage detected
– software watchdog timer
– 2.7V low-voltage detected (VREG)
– 2.7V low-voltage detected (flash)
– 2.7V low-voltage detected (I/O)
– comparator error
● A ‘functional’ reset source is associated with an event related to a less-critical - usually
non-hardware - error or dysfunction. When a ‘functional’ reset event occurs, a partial
reset sequence is applied to the device starting from PHASE1. In this case, most digital
modules are reset normally, while analog modules or specific digital modules’ (e.g.,
debug modules, flash modules) state is preserved. ‘Functional’ resets are
– external reset
– JTAG initiated reset
– core reset
– software reset
– checkstop reset
– PLL0 fail
– oscillator frequency lower than reference
– CMU0 clock frequency higher/lower than reference
– 4.5V low-voltage detected
– code or data flash fatal error
– PLL1 fail
When a reset is triggered, the MC_RGM state machine is activated and proceeds through
the different phases (i.e., PHASEn states). Each phase is associated with a particular
device reset being provided to the system. A phase is completed when all corresponding
To Next Page
Loading...
