RM0046 Clock Description
Doc ID 16912 Rev 5 103/936
Table 13. CR field descriptions
Field Description
IDF[3:0]
Input Division Factor
The value of this field sets the PLL input division factor.
0000: Divide by 1
0001: Divide by 2
0010: Divide by 3
0011: Divide by 4
0100: Divide by 5
0101: Divide by 6
0110: Divide by 7
0111: Divide by 8
1000: Divide by 9
1001: Divide by 10
1010: Divide by 11
1011: Divide by 12
1100: Divide by 13
1101: Divide by 14
1110: Divide by 15
1111: Clock Inhibit
ODF[1:0]
Output Division Factor
The value of this field sets the PLL output division factor.
00: Divide by 2
01: Divide by 4
10: Divide by 8
11: Divide by 16
NDIV[6:0]
Loop Division Factor
The value of this field sets the PLL loop division factor.
0000000–0011111: Reserved
0100000: Divide by 32
0100001: Divide by 33
0100010: Divide by 34
...
1011111: Divide by 95
1100000: Divide by 96
1100001–1111111: Reserved
en_pll_sw
This bit is used to enable progressive clock switching. After the PLL locks, the PLL output initially
is divided by 8, and then progressively decreases until it reaches divide-by-1.
Note: The PLL output should not be used if a non-changing clock is needed, such as for serial
communications, until the division has finished.
0: Progressive clock switching disabled
1: Progressive clock switching enabled
unlock_once
This bit is a sticky indication of PLL loss of lock condition. Unlock_once is set when the PLL loses
lock. Whenever the PLL reacquires lock, unlock_once remains set. unlock_once is cleared after a
POR event.
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