ST SPC560P34 - Static Random Access Memory (SRAM); Interrupt Controller (INTC)

Introduction RM0046
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● Read page sizes
– Code flash memory: 128 bits (4 words)
– Data flash memory: 32 bits (1 word)
● ECC with single-bit correction, double-bit detection for data integrity
– Code flash memory: 64-bit ECC
– Data flash memory: 32-bit ECC
● Embedded hardware program and erase algorithm
● Erase suspend and program abort
● Censorship protection scheme to prevent flash memory content visibility
● Hardware support for EEPROM emulation
1.6.5 Static random access memory (SRAM)
The SPC560P40/34 SRAM module provides up to 20 KB of general-purpose memory.
The SRAM module provides the following features:
● Supports read/write accesses mapped to the SRAM from any master
● Up to 20 KB general purpose SRAM
● Supports byte (8-bit), half word (16-bit), and word (32-bit) writes for optimal use of
memory
● Typical SRAM access time: no wait-state for reads and 32-bit writes; 1 wait-state for 8-
and 16-bit writes if back-to-back with a read to same memory block
1.6.6 Interrupt controller (INTC)
The interrupt controller (INTC) provides priority-based preemptive scheduling of interrupt
requests, suitable for statically scheduled hard real-time systems. The INTC handles 128
selectable-priority interrupt sources.
For high-priority interrupt requests, the time from the assertion of the interrupt request by
the peripheral to the execution of the interrupt service routine (ISR) by the processor has
been minimized. The INTC provides a unique vector for each interrupt request source for
quick determination of which ISR has to be executed. It also provides a wide number of
priorities so that lower priority ISRs do not delay the execution of higher priority ISRs. To
allow the appropriate priorities for each source of interrupt request, the priority of each
interrupt request is software configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be
supported. The INTC supports the priority ceiling protocol (PCP) for coherent accesses. By
providing a modifiable priority mask, the priority can be raised temporarily so that all tasks
which share the same resource can not preempt each other.
The INTC provides the following features:
● Unique 9-bit vector for each separate interrupt source
● 8 software triggerable interrupt sources
● 16 priority levels with fixed hardware arbitration within priority levels for each interrupt
source