ST SPC560P34 - Table 19. CMU_0_FDR Field Descriptions; Table 20. CMU_0_HFREFR_A Field Descriptions; Figure 21. Frequency Display Register (CMU_0_FDR); Figure 22. High Frequency Reference Register FMPLL_0 (CMU_0_HFREFR_A)

RM0046 Clock Description
Doc ID 16912 Rev 5 113/936
Frequency Display Register (CMU_0_FDR)
High Frequency Reference Register FMPLL_0 (CMU_0_HFREFR_A)
Figure 21. Frequency Display Register (CMU_0_FDR)
Address: Base + 0x0004 Access: User read-only
0123456789101112131415
R00000000 0000 FD[19:16]
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FD[15:0]
W
Reset0000000000000000
Table 19. CMU_0_FDR field descriptions
Field Description
FD[19:0]
Measured frequency bits
This register displays the measured frequency f
RC
with respect to f
OSC
. The measured value is given
by the following formula: f
RC
= (f
OSC
× MD) / n, where n is the value in CMU_FDR.
Figure 22. High Frequency Reference register FMPLL_0 (CMU_0_HFREFR_A)
Address: Base + 0x0008 Access: User read/write
0123456789101112131415
R00000000 00000 000
W
Reset0000000000000000
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R0000
HFREF[11:0]
W
Reset0000111111111111
Table 20. CMU_0_HFREFR_A field descriptions
Field Description
HFREF_A
High Frequency reference value
These bits determine the high reference value for the FMPLL_0 clock. The reference value is given
by: (HFREF_A[11:0]/16) × (f
RC
/4).