ST SPC560P34 - Page 887

RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 887/936
DBERC0 also controls which bits or fields in DBCR0–4 are reset by assertion of p_reset_b
when DBCR0
EDM
=1. Only software-owned bits or fields as shown in Table 465 are affected
in this case, except that DBCR0
RST
and DBSR
MRR
are updated by assertion of p_reset_b
regardless of the value of DBCR0
EDM
or DBERC0.
1 1 ——————1 1 —————————————— DBCR1
IAC12M
1 1 ————————1 —————————————
IAC3,
DBCR0
IAC3
,
DBCR1
IAC3US, IAC3ER
,
DBSR
IAC3
1 1 —————————1 ————————————
IAC4,
DBCR0
IAC4
,
DBCR1
IAC4US, IAC4ER
,
DBSR
IAC4
1 1 ————————1 1 ———————————— DBCR1
IAC34M
1 1 ——————————1 ———————————
DAC1, DVC1
DBCR0
DAC1
,
DBCR2
DAC1US, DAC1ER,
DVC1M, DVC1BE
DBCR4
DVC1C
DBSR
DAC1, DAC_OFST
1 1 ———————————1 ——————————
DAC2, DVC2
DBCR0
DAC2
,
DBCR2
DAC2US, DAC2ER,
DVC2M, DVC2BE
DBCR4
DVC2C
DBSR
DAC2, DAC_OFST
1 1 ——————————1 1 —————————— DBCR2
DAC12M
1 1 ——————1 ———1 ——————————— DBCR2
DAC1LNK
1 1 ————————1 ——1 —————————— DBCR2
DAC2LNK
1 1 ————————————1 —————————
DBCR0
RET
,
DBSR
RET
1 1 —————————————1 ————————DBCR0
DEVT1
, DBSR
DEVT1
1 1 ——————————————1 ———————DBCR0
DEVT2
, DBSR
DEVT2
1 1 —————————————————1 ————DBCR0
CIRPT
, DBSR
CIRPT
1 1 ——————————————————1 ———DBCR0
CRET
, DBSR
CRET
1 1 ———————————————————1 ——
1 1 —————————————————————1 DBCR0
FT
1. DBSR
MRR
is always updated by p_reset_b, regardless of the value of DBCR0
EDM
or DBERC0
IDM
Table 465. DBERC0 Resource Control (continued)
DBCR0
EDM
DBERC0
IDM
DBERC0
RST
DBERC0
UDE
DBERC0
ICMP
DBERC0
BRT
DBERC0
IRPT
DBERC0
TRAP
DBERC0
IAC1
DBERC0
IAC2
DBERC0
IAC3
DBERC0
IAC4
DBERC0
DAC1
DBERC0
DAC2
DBERC0
RET
DBERC0
DEVT1
DBERC0
DEVT2
DBERC0
CIRPT
DBERC0
CRET
DBERC0
BKPT
DBERC0
DQM
DBERC0
FT
Software Accessible via
mtspr,
affected by p_reset_b