RM0046 Mode Entry Module (MC_ME)
Doc ID 16912 Rev 5 157/936
16 MHz_IRC_SC
16 MHz_IRC State Change during mode transition indicator — This bit is set when the 16
MHz internal RC oscillator is requested to change its power up/down state. It is cleared when
the 16 MHz internal RC oscillator has completed its state change.
0 No state change is taking place
1A state change is taking place
SYSCLK_SW
System Clock Switching pending status —
0 No system clock source switching is pending
1A system clock source switching is pending
DFLASH_SC
DFLASH State Change during mode transition indicator — This bit is set when the DFLASH
is requested to change its power up/down state. It is cleared when the DFLASH has
completed its state change.
0 No state change is taking place
1A state change is taking place
CFLASH_SC
CFLASH State Change during mode transition indicator — This bit is set when the CFLASH
is requested to change its power up/down state. It is cleared when the DFLASH has
completed its state change.
0 No state change is taking place
1A state change is taking place
CDP_PRPH_0_143
Clock Disable Process Pending status for Peripherals 0…143 — This bit is set when any
peripheral has been requested to have its clock disabled. It is cleared when all the peripherals
which have been requested to have their clocks disabled have entered the state in which their
clocks may be disabled.
0 No peripheral clock disabling is pending
1Clock disabling is pending for at least one peripheral
CDP_PRPH_64_95
Clock Disable Process Pending status for Peripherals 64…95 — This bit is set when any
peripheral appearing in ME_PS2 has been requested to have its clock disabled. It is cleared
when all these peripherals which have been requested to have their clocks disabled have
entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1Clock disabling is pending for at least one peripheral
CDP_PRPH_32_63
Clock Disable Process Pending status for Peripherals 32…63 — This bit is set when any
peripheral appearing in ME_PS1 has been requested to have its clock disabled. It is cleared
when all these peripherals which have been requested to have their clocks disabled have
entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1Clock disabling is pending for at least one peripheral
CDP_PRPH_0_31
Clock Disable Process Pending status for Peripherals 0…31 — This bit is set when any
peripheral appearing in ME_PS0 has been requested to have its clock disabled. It is cleared
when all these peripherals which have been requested to have their clocks disabled have
entered the state in which their clocks may be disabled.
0 No peripheral clock disabling is pending
1Clock disabling is pending for at least one peripheral
Table 45. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions (continued)
Field Description
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