Deserial Serial Peripheral Interface (DSPI) RM0046
454/936 Doc ID 16912 Rev 5
2 Reserved
3
EOQF
End of queue flag
Indicates that transmission in progress is the last entry in a queue. The EOQF bit is set when the
TX FIFO entry has the EOQ bit set in the command halfword and after the last incoming databit is
sampled, but before the tASC delay starts. Refer to Section , “Classic SPI transfer format
(CPHA = 0) for details.
The EOQF bit is cleared by writing 1 to it. When the EOQF bit is set, the TXRXS bit is
automatically cleared.
0 EOQ is not set in the executing command.
1 EOQ bit is set in the executing SPI command.
EOQF does not function in slave mode.
4
TFUF
Transmit FIFO underflow flag
Indicates that an underflow condition in the TX FIFO has occurred. The transmit underflow
condition is detected only for DSPI modules operating in slave mode and SPI configuration. The
TFUF bit is set when the TX FIFO of a DSPI operating in SPI slave mode is empty, and a transfer
is initiated by an external SPI master. The TFUF bit is cleared by writing 1 to it.
0 TX FIFO underflow has not occurred.
1 TX FIFO underflow has occurred.
5 Reserved
6
TFFF
Transmit FIFO fill flag
Indicates that the TX FIFO can be filled. Provides a method for the DSPI to request more entries
to be added to the TX FIFO. The TFFF bit is set while the TX FIFO is not full. The TFFF bit can be
cleared by writing 1 to it, or an by acknowledgement from the eDMA controller when the TX FIFO
is full.
0 TX FIFO is full.
1 TX FIFO is not full.
7–11 Reserved
12
RFOF
Receive FIFO overflow flag
Indicates that an overflow condition in the RX FIFO has occurred. The bit is set when the RX FIFO
and shift register are full and a transfer is initiated. The bit is cleared by writing 1 to it.
0 RX FIFO overflow has not occurred.
1 RX FIFO overflow has occurred.
13 Reserved
14
RFDF
Receive FIFO drain flag
Indicates that the RX FIFO can be drained. Provides a method for the DSPI to request that entries
be removed from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF bit can be
cleared by writing 1 to it, or by acknowledgement from the eDMA controller when the RX FIFO is
empty.
0 RX FIFO is empty.
1 RX FIFO is not empty.
In the interrupt service routine, RFDF must be cleared only after the DSPIx_POPR register is read.
15 Reserved
Table 215. DSPIx_SR field descriptions (continued)
Field Description
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