e200z0 and e200z0h Core RM0046
274/936 Doc ID 16912 Rev 5
Instruction unit features
The features of the e200 Instruction unit are:
● 32-bit instruction fetch path supports fetching of one 32-bit instruction per clock, or as
many as two 16-bit VLE instructions per clock
● Instruction buffer with 4 entries in e200z0h, each holding a single 32-bit instruction, or a
pair of 16-bit instructions
● Instruction buffer with 2 entries in e200z0, each holding a single 32-bit instruction, or a
pair of 16-bit instructions
● Dedicated PC incrementer supporting instruction prefetches
● Branch unit with dedicated branch address adder supporting single cycle of execution
of certain branches, two cycles for all others
Integer unit features
The e200 integer unit supports single cycle execution of most integer instructions:
● 32-bit AU for arithmetic and comparison operations
● 32-bit LU for logical operations
● 32-bit priority encoder for count leading zero’s function
● 32-bit single cycle barrel shifter for shifts and rotates
● 32-bit mask unit for data masking and insertion
● Divider logic for signed and unsigned divide in 5 to 34 clocks with minimized execution
timing
● 8 × 32 hardware multiplier array supports 1 to 4 cycle 32 × 32 32 multiply (early out)
Load/Store unit features
The e200 load/store unit supports load, store, and the load multiple / store multiple
instructions:
● 32-bit effective address adder for data memory address calculations
● Pipelined operation supports throughput of one load or store operation per cycle
● 32-bit interface to memory (dedicated memory interface on e200z0h)
e200z0h system bus features
The features of the e200z0h System Bus interface are as follows:
● Independent Instruction and Data Buses
● AMBA AHB Lite Rev 2.0 Specification with support for ARM v6 AMBA Extensions
– Exclusive Access Monitor
– Byte Lane Strobes
– Cache Allocate Support
● 32-bit address bus plus attributes and control on each bus
● 32-bit read data bus for Instruction Interface
● Separate uni-directional 32-bit read data bus and 32-bit write data bus for Data
Interface
● Overlapped, in-order accesses
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