ST SPC560P34 - Page 348

Flash Memory RM0046
348/936 Doc ID 16912 Rev 5
TSLK
11
Test/Shadow Address Space Block Lock
This bit locks the block of Test and Shadow Address Space from program and Erase (Erase is any
case forbidden for Test block).
A value of 1 in the TSLK register signifies that the Test/Shadow block is locked for program and
Erase. A value of 0 in the TSLK register signifies that the Test/Shadow block is available to receive
program and Erase pulses.
The TSLK register is not writable once an interlock write is completed until MCR[DONE] is set at
the completion of the requested operation. Likewise, the TSLK register is not writable if a high
voltage operation is suspended.
Upon reset, information from the TestFlash block is loaded into the TSLK register. The TSLK bit
may be written as a register. Reset will cause the bit to go back to its TestFlash block value. The
default value of the TSLK bit (assuming erased fuses) would be locked.
TSLK is not writable unless LME is high.
0 Test/Shadow Address Space Block is unlocked and can be modified (if also SLL[STSLK] = 0).
1 Test/Shadow Address Space Block is locked and cannot be modified.
12:13
Reserved (Read Only)
A write to these bits has no effect. A read of these bits always outputs 0.
14:15 Reserved
LLK[15:0]
16:31
Low Address Space Block Lock 15-0
These bits lock the blocks of Low Address Space from program and Erase.
For code Flash, LLK[5:0] are related to sectors B0F[5:0], respectively. See Ta bl e 1 42 for more
information.
For data Flash, LLK[3:0] are related to sectors B1F[3:0], respectively. See Table 143 for more
information.
A value of 1 in a bit of the LLK bitfield signifies that the corresponding block is locked for program
and Erase.
A value of 0 in a bit of the LLK bitfield signifies that the corresponding block is available to receive
program and Erase pulses.
The LLK bitfield is not writable once an interlock write is completed until MCR[DONE] is set at the
completion of the requested operation. Likewise, the LLK bitfield is not writable if a high voltage
operation is suspended.
Upon reset, information from the TestFlash block is loaded into the LLK bitfields. The LLK bits
may be written as a register. Reset will cause the bits to go back to their TestFlash block value.
The default value of the LLK bits (assuming erased fuses) would be locked.
In the event that blocks are not present (due to configuration or total memory size), the LLK bits
will default to locked, and will not be writable. The reset value is always 1 (independent of the
TestFlash block), and register writes have no effect.
In the code Flash macrocell, bits LLK[15:6] are read-only and locked at 1.
In the data Flash macrocell, bits LLK[15:4] are read-only and locked at 1.
LLK is not writable unless LME is high.
0 Low Address Space Block is unlocked and can be modified (if also SLL[SLK] = 0).
1 Low Address Space Block is locked and cannot be modified.
1. This field is present only in LML
Table 151. LML and NVLML field descriptions (continued)
Field Description