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Introduction
RM0046
68/936
Doc ID 16912 Rev 5
SPC560P40/34 f
amily members ar
e off
ered in the f
ollowing pac
kage types:
●
64-pin LQFP
, 0.5
mm pitch, 10
mm
×
10
mm outline
●
100-pin LQFP
, 0.5
mm pitch, 14
mm
×
14
mm outline
67
69
Table of Contents
Main Page
Default Chapter
2
Table of Contents
2
Preface
45
Overview
45
Audience
45
Chapter Organization and Device-Specific Information
45
References
45
Introduction
46
The SPC560P40/34 Microcontroller Family
46
Target Applications
47
Application Examples
47
Figure 1. Electric Power Steering Application
47
Features
48
Table 1. SPC560P40/34 Device Comparison
48
Figure 2. Airbag Application
48
Table 2. SPC560P40 Device Configuration Differences
50
Figure 3. Block Diagram (SPC560P40 Full-Featured Configuration)
51
Critical Performance Parameters
52
Chip-Level Features
52
Module Features
53
High Performance E200Z0 Core Processor
53
Crossbar Switch (XBAR)
54
Enhanced Direct Memory Access (Edma)
54
Flash Memory
55
Static Random Access Memory (SRAM)
56
Interrupt Controller (INTC)
56
System Status and Configuration Module (SSCM)
57
System Clocks and Clock Generation
57
Frequency-Modulated Phase-Locked Loop (FMPLL)
57
Main Oscillator
58
Internal RC Oscillator
58
Periodic Interrupt Timer (PIT)
58
System Timer Module (STM)
58
Software Watchdog Timer (SWT)
58
Fault Collection Unit (FCU)
59
System Integration Unit - Lite (SIUL)
59
Boot and Censorship
59
Error Correction Status Module (ECSM)
60
Peripheral Bridge (PBRIDGE)
60
Controller Area Network (Flexcan)
60
Safety Port (Flexcan)
61
Serial Communication Interface Module (Linflex)
62
Deserial Serial Peripheral Interface (DSPI)
62
Pulse Width Modulator (Flexpwm)
63
Etimer
64
Analog-To-Digital Converter (ADC) Module
65
Cross Triggering Unit (CTU)
65
Nexus Development Interface (NDI)
66
Cyclic Redundancy Check (CRC)
66
IEEE 1149.1 JTAG Controller
66
On-Chip Voltage Regulator (VREG)
67
Developer Environment
67
Package
67
SPC560P40/34 Memory Map
69
Table 3. Memory Map
69
Signal Description
72
100-Pin LQFP Pinout
72
Figure 4. 100-Pin LQFP Pinout - Full Featured Configuration (Top View)
72
Figure 5. 100-Pin LQFP Pinout - Airbag Configuration (Top View)
73
64-Pin LQFP Pinout
74
Figure 6. 64-Pin LQFP Pinout - Full Featured Configuration (Top View)
74
Pin Description
75
Power Supply and Reference Voltage Pins
75
Figure 7. 64-Pin LQFP Pinout - Airbag Configuration (Top View)
75
System Pins
76
Table 4. Supply Pins
76
Pin Multiplexing
77
Table 5. System Pins
77
Table 6. Pin Muxing
78
CTU / ADC / Flexpwm / Etimer Connections
88
Table 7. CTU / ADC / Flexpwm / Etimer Connections
88
Figure 8. CTU / ADC / Flexpwm / Etimer Connections
88
Clock Description
91
Clock Architecture
91
Figure 9. SPC560P40/34 System Clock Generation
92
Figure 10. SPC560P40/34 System Clock Distribution Part a
93
Available Clock Domains
94
FMPLL Input Reference Clock
94
Figure 11. SPC560P40/34 System Clock Distribution Part B
94
Clock Selectors
95
Auxiliary Clock Selector 0
95
Auxiliary Clock Selector 1
95
Auxiliary Clock Selector 2
95
Auxiliary Clock Dividers
95
External Clock Divider
95
Alternate Module Clock Domains
96
Flexcan Clock Domains
96
SWT Clock Domains
96
Cross Triggering Unit (CTU) Clock Domains
96
Peripherals Behind the IPS Bus Clock Sync Bridge
96
Clock Behavior in STOP and HALT Mode
97
System Clock Functional Safety
97
IRC 16 Mhz Internal RC Oscillator (RC_CTL)
98
XOSC External Crystal Oscillator
98
Figure 12. RC Control Register (RC_CTL)
98
Table 8. RC_CTL Field Descriptions
98
Functional Description
99
Register Description
99
Table 10. OSC_CTL Memory Map
99
Table 9. Crystal Oscillator Truth Table
99
Frequency Modulated Phase Locked Loop (FMPLL)
100
Introduction
100
Table 11. OSC_CTL Field Descriptions
100
Figure 13. Crystal Oscillator Control Register (OSC_CTL)
100
Overview
101
Features
101
Memory Map
101
Figure 14. FMPLL Block Diagram
101
Register Description
102
Table 12. FMPLL Memory Map
102
Figure 15. Control Register (CR)
102
Table 13. CR Field Descriptions
103
Table 14. MR Field Descriptions
104
Figure 16. Modulation Register (MR)
104
Functional Description
105
Table 15. Progressive Clock Switching on Pll_Select Rising Edge
106
Figure 17. Progressive Clock Switching Scheme
106
Recommendations
108
Clock Monitor Unit (CMU)
108
Overview
108
Figure 18. Frequency Modulation Depth Spreads
108
Main Features
109
Table 16. CMU Module Summary
109
Figure 19. SPC560P40/34CMU
109
Functional Description
110
Memory Map and Register Description
111
Table 17. CMU Memory Map
111
Table 18. CMU_0_CSR Field Descriptions
112
Figure 20. Control Status Register (CMU_0_CSR)
112
Table 19. CMU_0_FDR Field Descriptions
113
Table 20. CMU_0_HFREFR_A Field Descriptions
113
Figure 21. Frequency Display Register (CMU_0_FDR)
113
Figure 22. High Frequency Reference Register FMPLL_0 (CMU_0_HFREFR_A)
113
Table 21. CMU_0_LFREFR_A Fields Descriptions
114
Table 22. CMU_0_ISR Field Descriptions
114
Figure 23. Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A)
114
Figure 24. Interrupt Status Register (CMU_0_ISR)
114
Table 23. CMU_0_MDR Field Descriptions
115
Figure 25. Measurement Duration Register (CMU_0_MDR)
115
Clock Generation Module (MC_CGM)
116
Overview
116
Figure 26. MC_CGM Block Diagram
117
Features
118
External Signal Description
118
Memory Map and Register Definition
118
Table 24. MC_CGM Register Description
118
Table 25. MC_CGM Memory Map
119
Register Descriptions
123
Output Clock Enable Register (CGM_OC_EN)
124
Output Clock Division Select Register (CGM_OCDS_SC)
124
Table 26. Output Clock Enable Register (CGM_OC_EN) Field Descriptions
124
Figure 27. Output Clock Enable Register (CGM_OC_EN)
124
Figure 28. Output Clock Division Select Register (CGM_OCDS_SC)
124
System Clock Select Status Register (CGM_SC_SS)
125
Table 27. Output Clock Division Select Register (CGM_OCDS_SC) Field Descriptions
125
Figure 29. System Clock Select Status Register (CGM_SC_SS)
125
System Clock Divider Configuration Register (CGM_SC_DC0)
126
Table 28. System Clock Select Status Register (CGM_SC_SS) Field Descriptions
126
Table 29. System Clock Divider Configuration Register (CGM_SC_DC0) Field Descriptions
126
Figure 30. System Clock Divider Configuration Register (CGM_SC_DC0)
126
Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)
127
Table 30. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) Field Descriptions
127
Figure 31. Auxiliary Clock 0 Select Control Register (CGM_AC0_SC)
127
Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0)
128
Auxiliary Clock 1 Select Control Register (CGM_AC1_SC)
128
Table 31. Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) Field Descriptions
128
Figure 32. Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0)
128
Figure 33. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC)
128
Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)
129
Table 32. Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) Field Descriptions
129
Table 33. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) Field Descriptions
129
Figure 34. Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0)
129
Auxiliary Clock 2 Select Control Register (CGM_AC2_SC)
130
Table 34. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) Field Descriptions
130
Figure 35. Auxiliary Clock 2 Select Control Register (CGM_AC2_SC)
130
Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)
131
Functional Description
131
System Clock Generation
131
Figure 36. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0)
131
Table 35. Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) Field Descriptions
131
System Clock Disable
132
System Clock Dividers
132
System Clock Source Selection
132
Auxiliary Clock Generation
132
Figure 37. MC_CGM System Clock Generation Overview
132
Figure 38. MC_CGM Auxiliary Clock 0 Generation Overview
133
Figure 39. MC_CGM Auxiliary Clock 1 Generation Overview
133
Auxiliary Clock Dividers
134
Auxiliary Clock Source Selection
134
Dividers Functional Description
134
Figure 40. MC_CGM Auxiliary Clock 2 Generation Overview
134
Output Clock Multiplexing
135
Output Clock Division Selection
135
Figure 41. MC_CGM Output Clock Multiplexer and PAD[22] Generation
135
Mode Entry Module (MC_ME)
136
Introduction
136
Overview
136
Figure 42. MC_ME Block Diagram
137
Features
138
Modes of Operation
138
Table 36. MC_ME Mode Descriptions
138
External Signal Description
139
Memory Map and Register Definition
139
Memory Map
139
Table 37. MC_ME Register Description
139
Table 38. MC_ME Memory Map
142
Register Description
146
Table 39. Global Status Register (ME_GS) Field Descriptions
147
Figure 43. Global Status Register (ME_GS)
147
Figure 44. Mode Control Register (ME_MCTL)
149
Table 40. Mode Control Register (ME_MCTL) Field Descriptions
150
Figure 45. Mode Enable Register (ME_ME)
150
Table 41. Mode Enable Register (ME_ME) Field Descriptions
151
Table 42. Interrupt Status Register (ME_IS) Field Descriptions
152
Figure 46. Interrupt Status Register (ME_IS)
152
Table 43. Interrupt Mask Register (ME_IM) Field Descriptions
153
Figure 47. Interrupt Mask Register (ME_IM)
153
Table 44. Invalid Mode Transition Status Register (ME_IMTS) Field Descriptions
154
Figure 48. Invalid Mode Transition Status Register (ME_IMTS)
154
Figure 49. Debug Mode Transition Status Register (ME_DMTS)
155
Table 45. Debug Mode Transition Status Register (ME_DMTS) Field Descriptions
156
Figure 50. RESET Mode Configuration Register (ME_RESET_MC)
158
Figure 51. TEST Mode Configuration Register (ME_TEST_MC)
158
Figure 52. SAFE Mode Configuration Register (ME_SAFE_MC)
159
Figure 53. DRUN Mode Configuration Register (ME_DRUN_MC)
160
Figure 54. RUN0
161
Figure 55. HALT0 Mode Configuration Register (ME_HALT0_MC)
161
Table 46. Mode Configuration Registers (Me_<Mode>_Mc) Field Descriptions
162
Figure 56. STOP0 Mode Configuration Register (ME_STOP0_MC)
162
Figure 58. Peripheral Status Register 1 (ME_PS1)
164
Table 47. Peripheral Status Registers 0
165
Figure 59. Peripheral Status Register 2 (ME_PS2)
165
Table 47. Peripheral Status Registers 0...4 (ME_PS0...4) Field Descriptions
165
Table 48. Run Peripheral Configuration Registers (ME_RUN_PC0
166
Table 48. Run Peripheral Configuration Registers (ME_RUN_PC0...7) Field Descriptions
166
Table 49. Low-Power Peripheral Configuration Registers (ME_LP_PC0
167
Figure 61. Low-Power Peripheral Configuration Registers (ME_LP_PC0
167
Figure 62. Peripheral Control Registers (ME_PCTL0
167
Functional Description
168
Mode Transition Request
168
Table 50. Peripheral Control Registers (ME_PCTL0
168
Modes Details
169
Figure 63. MC_ME Mode Diagram
169
Mode Transition Process
172
Table 51. MC_ME Resource Control Overview
173
Table 52. MC_ME System Clock Selection Overview
177
Figure 64. MC_ME Transition Diagram
179
Protection of Mode Configuration Registers
180
Mode Transition Interrupts
180
Peripheral Clock Gating
182
Application Example
182
Figure 65. MC_ME Application Example Flow Diagram
183
Power Control Unit (MC_PCU)
184
Introduction
184
Overview
184
Features
184
Figure 66. MC_PCU Block Diagram
184
External Signal Description
185
Memory Map and Register Definition
185
Memory Map
185
Table 53. MC_PCU Register Description
185
Table 54. MC_PCU Memory Map
185
Register Descriptions
186
Table 55. Power Domain Status Register (PCU_PSTAT) Field Descriptions
186
Figure 67. Power Domain Status Register (PCU_PSTAT)
186
Reset Generation Module (MC_RGM)
187
Introduction
187
Overview
187
Figure 68. MC_RGM Block Diagram
188
Features
189
Reset Sources
189
External Signal Description
190
Memory Map and Register Definition
190
Table 56. MC_RGM Register Description
190
Table 57. MC_RGM Memory Map
191
Figure 69. Functional Event Status Register (RGM_FES)
192
Register Descriptions
192
Table 58. Functional Event Status Register (RGM_FES) Field Descriptions
193
Figure 70. Destructive Event Status Register (RGM_DES)
194
Table 59. Destructive Event Status Register (RGM_DES) Field Descriptions
194
Figure 71. Functional Event Reset Disable Register (RGM_FERD)
196
Table 60. Functional Event Reset Disable Register (RGM_FERD) Field Descriptions
196
Figure 72. Destructive Event Reset Disable Register (RGM_DERD)
197
Table 61. Destructive Event Reset Disable Register (RGM_DERD) Field Descriptions
197
Figure 73. Functional Event Alternate Request Register (RGM_FEAR)
198
Table 62. Functional Event Alternate Request Register (RGM_FEAR) Field Descriptions
198
Figure 74. Functional Event Short Sequence Register (RGM_FESS)
199
Table 63. Functional Event Short Sequence Register (RGM_FESS) Field Descriptions
199
Figure 75. Functional Bidirectional Reset Enable Register (RGM_FBRE)
200
Table 64. Functional Bidirectional Reset Enable Register (RGM_FBRE) Field Descriptions
201
Functional Description
202
Reset State Machine
202
Table 65. MC_RGM Reset Implications
202
Figure 76. MC_RGM State Machine
203
Destructive Resets
204
External Reset
205
Functional Resets
205
Alternate Event Generation
206
Boot Mode Capturing
206
Table 66. MC_RGM Alternate Event Selection
206
Interrupt Controller (INTC)
208
Introduction
208
Features
208
Table 67. Interrupt Sources Available
209
Block Diagram
210
Modes of Operation
210
Normal Mode
210
Figure 77. INTC Block Diagram
210
Memory Map and Registers Description
212
Module Memory Map
212
Registers Description
212
Table 68. INTC Memory Map
212
Table 69. INTC_MCR Field Descriptions
213
Figure 78. INTC Module Configuration Register (INTC_MCR)
213
Figure 79. INTC Current Priority Register (INTC_CPR)
213
Table 70. INTC_CPR Field Descriptions
214
Table 71. INTC_IACKR Field Descriptions
215
Figure 80. INTC Interrupt Acknowledge Register (INTC_IACKR)
215
Figure 81. INTC End-Of-Interrupt Register (INTC_EOIR)
216
Figure 82. INTC Software Set/Clear Interrupt Register 0-3 (INTC_SSCIR[0:3])
216
Table 72. INTC_SSCIR[0:7] Field Descriptions
217
Figure 83. INTC Software Set/Clear Interrupt Register 4-7 (INTC_SSCIR[4:7])
217
Table 73. INTC_PSR0_3-INTC_PSR220-221 Field Descriptions
218
Table 74. INTC Priority Select Register Address Offsets
218
Figure 84. INTC Priority Select Register 0-3 (INTC_PSR[0:3])
218
Figure 85. INTC Priority Select Register 220-221 (INTC_PSR[220:221])
218
Functional Description
220
Table 75. Interrupt Vector Table
220
Interrupt Request Sources
228
Priority Management
228
Handshaking with Processor
230
Figure 86. Software Vector Mode Handshaking Timing Diagram
231
Initialization/Application Information
232
Initialization Flow
232
Interrupt Exception Handler
232
Figure 87. Hardware Vector Mode Handshaking Timing Diagram
232
ISR, RTOS, and Task Hierarchy
234
Order of Execution
235
Table 76. Order of ISR Execution Example
235
Priority Ceiling Protocol
236
Selecting Priorities According to Request Rates and Deadlines
237
Software Configurable Interrupt Requests
237
Lowering Priority Within an ISR
238
Negating an Interrupt Request Outside of Its ISR
238
Examining LIFO Contents
239
System Status and Configuration Module (SSCM)
240
Introduction
240
Overview
240
Features
240
Figure 88. SSCM Block Diagram
240
Modes of Operation
241
Memory Map and Register Description
241
Memory Map
241
Register Description
241
Table 77. SSCM Memory Map
241
Figure 89. Key to Register Fields
241
Table 78. STATUS Allowed Register Accesses
242
Table 79. STATUS Field Descriptions
242
Figure 90. Status (STATUS) Register
242
Table 80. MEMCONFIG Field Descriptions
243
Table 81. MEMCONFIG Allowed Register Accesses
243
Figure 91. System Memory Configuration (MEMCONFIG) Register
243
Table 82. ERROR Field Descriptions
244
Table 83. ERROR Allowed Register Accesses
244
Figure 92. Error Configuration (ERROR) Register
244
Table 84. DEBUGPORT Field Descriptions
245
Table 85. Debug Status Port Modes
245
Figure 93. Debug Status Port (DEBUGPORT) Register
245
Table 86. DEBUGPORT Allowed Register Accesses
246
Table 87. PWCMPH/L Field Descriptions
246
Figure 94. Password Comparison Register High Word (PWCMPH) Register
246
Figure 95. Password Comparison Register Low Word (PWCMPL) Register
246
Functional Description
247
Initialization/Application Information
247
Reset
247
Table 88. PWCMPH/L Allowed Register Accesses
247
System Integration Unit Lite (SIUL)
248
Introduction
248
Overview
248
Features
249
Figure 96. System Integration Unit Lite Block Diagram
249
Register Protection
250
External Signal Description
250
Detailed Signal Descriptions
250
Table 89. SIUL Signal Properties
250
Memory Map and Register Description
251
SIUL Memory Map
251
Table 90. SIUL Memory Map
251
Register Description
252
Figure 97. Key to Register Fields
252
Figure 98. MCU ID Register #1 (MIDR1)
252
Table 91. MIDR1 Field Descriptions
253
Table 92. MIDR2 Field Descriptions
254
Figure 99. MCU ID Register #2 (MIDR2)
254
Table 93. ISR Field Descriptions
255
Table 94. IRER Field Descriptions
255
Figure 100. Interrupt Status Flag Register (ISR)
255
Figure 101. Interrupt Request Enable Register (IRER)
255
Table 95. IREER Field Descriptions
256
Table 96. IFEER Field Descriptions
256
Figure 102. Interrupt Rising-Edge Event Enable Register (IREER)
256
Figure 103. Interrupt Falling-Edge Event Enable Register (IFEER)
256
Table 97. IFER Field Descriptions
257
Figure 104. Interrupt Filter Enable Register (IFER)
257
Figure 105. Pad Configuration Registers 0-71 (PCR[0:71])
257
Table 98. PCR[0:71] Field Descriptions
258
Table 99. Pcr[N] Reset Value Exceptions
259
Table 100. PCR Bit Implementation by Pad Type
259
Table 101. PSMI[0_3:32_35] Field Descriptions
260
Table 102. Pad Selection
260
Figure 106. Pad Selection for Multiplexed Inputs Registers (PSMI[0_3:32_35])
260
Table 103. GPDO[0_3:68_71] Field Descriptions
262
Figure 107. Port GPIO Pad Data Output Registers 0_3-68_71 (GPDO[0_3:68_71])
262
Figure 108. GPIO Pad Data Input Registers 0_3-68_71 (GPDI[0_3:68_71])
262
Table 104. GPDI[0_3:68_71] Field Descriptions
263
Table 105. PGPDO0_3 Field Descriptions
263
Figure 109. Parallel GPIO Pad Data out Register 0-3(PGPDO[0:3])
263
Table 106. PGPDI[0:3] Field Descriptions
264
Figure 110. Parallel GPIO Pad Data in Register 0-3 (PGPDI[0:3])
264
Figure 111. Masked Parallel GPIO Pad Data out Register 0-6 (MPGPDO[0:6])
264
Table 107. MPGPDO[0:6] Field Descriptions
265
Table 108. IFMC[0:24] Field Descriptions
265
Figure 112. Interrupt Filter Maximum Counter Registers 0-24 (IFMC[0:24])
265
Table 109. IFCPR Field Descriptions
266
Figure 113. Interrupt Filter Clock Prescaler Register
266
Functional Description
267
General
267
Pad Control
267
General Purpose Input and Output Pads (GPIO)
267
Figure 114. Data Port Example Arrangement Showing Configuration for Different Port Width Accesses
267
External Interrupts
268
Figure 115. External Interrupt Pad Diagram
268
Pin Muxing
269
E200Z0 and E200Z0H Core
270
Overview
270
Features
270
Microarchitecture Summary
271
Figure 116. E200Z0 Block Diagram
272
Figure 117. E200Z0H Block Diagram
273
Core Registers and Programmer's Model
275
Figure 118. E200Z0 Supervisor Mode Programmer's Model
276
Figure 119. E200Z0H Supervisor Mode Programmer's Model
277
Unimplemented Sprs and Read-Only Sprs
278
Instruction Summary
278
Figure 120. E200 User Mode Program Model
278
Peripheral Bridge (PBRIDGE)
279
Introduction
279
Block Diagram
279
Overview
279
Modes of Operation
279
Figure 121. PBRIDGE Interface
279
Functional Description
280
Access Support
280
General Operation
280
Crossbar Switch (XBAR)
281
Introduction
281
Block Diagram
281
Table 110. Device XBAR Switch Ports
281
Figure 122. XBAR Block Diagram
281
Overview
282
Features
282
Modes of Operation
282
Normal Mode
282
Debug Mode
282
Functional Description
282
General Operation
283
Master Ports
283
Slave Ports
284
Priority Assignment
284
Arbitration
284
Table 111. Hardwired Bus Master Priorities
284
Error Correction Status Module (ECSM)
286
Introduction
286
Overview
286
Features
286
Memory Map and Registers Description
286
Memory Map
287
Table 112. ECSM Registers
287
Registers Description
288
Table 113. PCT Field Descriptions
288
Figure 123. Processor Core Type (PCT) Register
288
Figure 124. Revision (REV) Register
288
Table 114. REV Field Descriptions
289
Table 115. PLAMC Field Descriptions
289
Figure 125. Platform XBAR Master Configuration (PLAMC) Register
289
Figure 126. Platform XBAR Slave Configuration (PLASC) Register
289
Table 116. ASC Field Descriptions
290
Table 117. IMC Field Descriptions
290
Figure 127. IPS Module Configuration (IMC) Register
290
Table 118. MRSR Field Descriptions
291
Table 119. mir Field Descriptions
291
Figure 128. Miscellaneous Reset Status Register (MRSR)
291
Figure 129. Miscellaneous Interrupt Register (MIR)
291
Table 120. MUDCR Field Descriptions
292
Figure 130. Miscellaneous User-Defined Control Register (MUDCR)
292
Figure 131. ECC Configuration Register (ECR)
293
Table 121. ECR Field Descriptions
294
Table 122. ESR Field Descriptions
295
Figure 132. ECC Status Register (ESR)
295
Figure 133. ECC Error Generation Register (EEGR)
296
Table 123. EEGR Field Descriptions
297
Table 124. FEAR Field Descriptions
299
Table 125. FEMR Field Descriptions
299
Figure 134. Flash ECC Address Register (FEAR)
299
Figure 135. Flash ECC Master Number Register (FEMR)
299
Table 126. FEAT Field Descriptions
300
Figure 136. Flash ECC Attributes (FEAT) Register
300
Table 127. FEDR Field Descriptions
301
Figure 137. Flash ECC Data Register (FEDR)
301
Figure 138. RAM ECC Address Register (REAR)
301
Table 128. REAR Field Descriptions
302
Table 129. RESR Field Descriptions
302
Table 130. RAM Syndrome Mapping for Single-Bit Correctable Errors
302
Figure 139. RAM ECC Syndrome Register (RESR)
302
Table 131. REMR Field Descriptions
304
Figure 140. RAM ECC Master Number Register (REMR)
304
Table 132. REAT Field Descriptions
305
Figure 141. RAM ECC Attributes (REAT) Register
305
Ecsm_Reg_Protection
306
Table 133. REDR Field Descriptions
306
Figure 142. Platform RAM ECC Data Register (PREDR)
306
Figure 143. Spp_Ips_Reg_Protection Block Diagram
307
Internal Static RAM (SRAM)
308
Introduction
308
SRAM Operating Mode
308
Module Memory Map
308
Register Descriptions
308
SRAM ECC Mechanism
308
Table 134. SRAM Operating Modes
308
Table 135. SRAM Memory Map
308
Access Timing
309
Table 136. Number of Wait States Required for SRAM Operations
309
Reset Effects on SRAM Accesses
310
Functional Description
310
Initialization and Application Information
310
Flash Memory
311
Introduction
311
Platform Flash Controller
311
Figure 144. SPC560P40/34 Flash Memory Architecture
311
External Signal Descriptions
313
Memory Map and Registers Description
313
Modes of Operation
313
Table 137. Flash-Related Regions in the System Memory Map
314
Basic Interface Protocol
315
Functional Description
315
Table 138. Platform Flash Controller 32-Bit Memory Map
315
Access Protections
316
Read Cycles - Buffer Hit
316
Read Cycles - Buffer Miss
316
Access Pipelining
317
Error Termination
317
Write Cycles
317
Bank0 Page Read Buffers and Prefetch Operation
318
Flash Error Response Operation
318
Bank1 Temporary Holding Register
320
Read-While-Write Functionality
321
Table 139. Platform Flash Controller Stall-While-Write Interrupts
322
Wait State Emulation
322
Table 140. Additional Wait State Encoding
323
Table 141. Extended Additional Wait State Encoding
323
Timing Diagrams
323
Figure 145. 1-Cycle Access, no Buffering, no Prefetch
324
Figure 146. 3-Cycle Access, no Prefetch, Buffering Disabled
325
Figure 147. 3-Cycle Access, no Prefetch, Buffering Enabled
326
Figure 148. 3-Cycle Access, Prefetch and Buffering Enabled
327
Figure 149. 3-Cycle Access, Stall-And-Retry with Bkn_Rwwc = 11X
328
Figure 150. 3-Cycle Access, Terminate-And-Retry with Bkn_Rwwc = 10X
329
Flash Memory
330
Introduction
330
Main Features
330
Block Diagram
330
Figure 151. Data Flash Module Structure
331
Functional Description
332
Figure 152. Code Flash Module Structure
332
Table 142. 288 KB Code Flash Module Sectorization
333
Table 143. 64 KB Data Flash Module Sectorization
333
Table 144. Testflash Structure
334
Operating Modes
336
Table 145. Shadow Sector Structure
336
Registers Description
339
Register Map
339
Table 146. Flash Registers
339
Table 147. Flash 256 KB Bank0 Register Map
339
Table 148. Flash 64 KB Bank1 Register Map
341
Table 149. MCR Field Descriptions
342
Figure 153. Module Configuration Register (MCR)
342
Table 150. MCR Bits Set/Clear Priority Levels
346
Table 151. LML and NVLML Field Descriptions
347
Figure 154. Low/MID Address Space Block Locking Register (LML)
347
Figure 155. Non-Volatile Low/MID Address Space Block Locking Register (NVLML)
347
Figure 156. Secondary Low/MID Address Space Block Locking Reg (SLL)
349
Figure 157. Non-Volatile Secondary Low/MID Address Space Block Locking Register (NVSLL)
349
Table 152. SLL and NVSLL Field Descriptions
350
Figure 158. Low/MID Address Space Block Select Register (LMS)
351
Table 153. LMS Field Descriptions
352
Table 154. ADR Field Descriptions
352
Figure 159. Address Register (ADR)
352
Table 155. ADR Content: Priority List
353
Table 156. PFCR0 Field Descriptions
354
Figure 160. Platform Flash Configuration Register 0 (PFCR0)
354
Table 157. PFCR1 Field Descriptions
357
Figure 161. Platform Flash Configuration Register 1 (PFCR1)
357
Table 158. PFAPR Field Descriptions
359
Figure 162. Platform Flash Access Protection Register (PFAPR)
359
Figure 163. User Test 0 Register (UT0)
360
Table 159. UT0 Field Descriptions
361
Figure 164. User Test 1 Register (UT1)
362
Table 160. UT1 Field Descriptions
363
Table 161. UT2 Field Descriptions
363
Figure 165. User Test 2 Register (UT2)
363
Table 162. UMSIR0 Field Descriptions
364
Table 163. UMISR1 Field Descriptions
364
Figure 166. User Multiple Input Signature Register 0 (UMISR0)
364
Figure 167. User Multiple Input Signature Register 1 (UMISR1)
364
Table 164. UMISR2 Field Descriptions
365
Figure 168. User Multiple Input Signature Register 2 (UMISR2)
365
Table 165. UMISR3 Field Descriptions
366
Figure 169. User Multiple Input Signature Register 3 (UMISR3)
366
Figure 170. User Multiple Input Signature Register 4 (UMISR4)
366
Table 166. UMISR4 Field Descriptions
367
Table 167. NVPWD0 Field Descriptions
367
Figure 171. Non-Volatile Private Censorship Password 0 Register (NVPWD0)
367
Table 168. NVPWD1 Field Descriptions
368
Table 169. NVSCI0 Field Descriptions
368
Figure 172. Non-Volatile Private Censorship Password 1 Register (NVPWD1)
368
Figure 173. Non-Volatile System Censoring Information 0 Register (NVSCI0)
368
Table 170. NVSCI1 Field Descriptions
369
Figure 174. Non-Volatile System Censoring Information 1 Register (NVSCI1)
369
Code Flash Programming Considerations
370
Table 171. NVUSRO Field Descriptions
370
Figure 175. Non-Volatile User Options Register (NVUSRO)
370
Table 172. Flash Modify Operations
371
Table 173. Bits Manipulation: Double Words with the same ECC Value
379
Table 174. Bits Manipulation: Censorship Management
381
Enhanced Direct Memory Access (Edma)
382
Introduction
382
Overview
382
Figure 176. Edma Block Diagram
382
Features
383
Modes of Operation
383
Normal Mode
383
Debug Mode
384
Memory Map and Register Definition
384
Memory Map
384
Table 175. Edma Memory Map
384
Register Descriptions
386
Figure 177. Edma Control Register (EDMA_CR)
386
Table 176. EDMA_CR Field Descriptions
387
Table 177. EDMA_ESR Field Descriptions
388
Figure 178. Edma Error Status Register (EDMA_ESR)
388
Table 178. EDMA_ERQRL Field Descriptions
390
Figure 179. Edma Enable Request Low Register (EDMA_ERQRL)
390
Table 179. EDMA_EEIRL Field Descriptions
391
Table 180. EDMA_SERQR Field Descriptions
391
Figure 180. Edma Enable Error Interrupt Low Register (EDMA_EEIRL)
391
Figure 181. Edma Set Enable Request Register (EDMA_SERQR)
391
Table 181. EDMA_CERQR Field Descriptions
392
Figure 182. Edma Clear Enable Request Register (EDMA_CERQR)
392
Figure 183. Edma Set Enable Error Interrupt Register (EDMA_SEEIR)
392
Table 182. EDMA_SEEIR Field Descriptions
393
Table 183. EDMA_CEEIR Field Descriptions
393
Figure 184. Edma Set Enable Error Interrupt Register (EDMA_SEEIR)
393
Table 184. EDMA_CIRQR Field Descriptions
394
Table 185. EDMA_CERR Field Descriptions
394
Figure 185. Edma Clear Interrupt Request (EDMA_CIRQR)
394
Figure 186. Edma Clear Error Register (EDMA_CERR)
394
Table 186. EDMA_SSBR Field Descriptions
395
Figure 187. Edma Set START Bit Register (EDMA_SSBR)
395
Figure 188. Edma Clear DONE Status Bit Register (EDMA_CDSBR)
395
Table 187. EDMA_CDSBR Field Descriptions
396
Table 188. EDMA_IRQRL Field Descriptions
396
Figure 189. Edma Interrupt Request Low Register (EDMA_IRQRL)
396
Table 189. EDMA_ERL Field Descriptions
397
Figure 190. Edma Error Low Register (EDMA_ERL)
397
Table 190. EDMA_HRSL Field Descriptions
398
Figure 191. EDMA Hardware Request Status Register Low (EDMA_HRSL)
398
Table 191. Edma_Cprn Field Descriptions
399
Table 192. Tcdn 32-Bit Memory Structure
399
Figure 192. Edma Channel N Priority Register (Edma_Cprn)
399
Table 193. Tcdn Field Descriptions
401
Figure 193. TCD Structure
401
Functional Description
406
Edma Microarchitecture
406
Edma Basic Data Flow
407
Figure 194. Edma Operation, Part 1
408
Figure 195. Edma Operation, Part 2
409
Edma Performance
410
Figure 196. Edma Operation, Part 3
410
Table 194. Edma Peak Transfer Rates (Mb/Sec)
411
Table 195. Edma Peak Request Rate (Mreq/Sec)
412
Initialization / Application Information
414
Edma Initialization
414
Table 196. TCD Primary Control and Status Fields
414
Figure 197. Example of Multiple Loop Iterations
415
DMA Programming Errors
416
DMA Request Assignments
416
Table 197. DMA Request Summary for Edma
416
Figure 198. Memory Array Terms
416
DMA Arbitration Mode Considerations
417
Table 198. Modulo Feature Example
420
TCD Status
421
Channel Linking
422
Table 199. Channel Linking Parameters
423
Dynamic Programming
423
Figure 199. DMA Mux Block Diagram
424
DMA Channel Mux (DMA_MUX)
424
Table 200. DMA_MUX Memory Map
425
Modes of Operation
425
Table 201. Chconfig#X Field Descriptions
427
Table 202. Channel and Trigger Enabling
427
Figure 200. Channel Configuration Registers (Chconfig#N)
427
Register Descriptions
427
Table 203. DMA Channel Mapping
428
DMA Request Mapping
428
Functional Description
429
Figure 201. DMA Mux Triggered Channels Diagram
430
Figure 202. DMA Mux Channel Triggering: Normal Operation
430
Figure 203. DMA Mux Channel Triggering: Ignored Trigger
431
DMA Channels with no Triggering Capability
432
Deserial Serial Peripheral Interface (DSPI)
437
Figure 205. DSPI Block Diagram
437
Figure 206. DSPI with Queues and Edma
438
Overview
438
Modes of Operation
439
Figure 204. DMA Mux Channel 4-15 Block Diagram
432
Master Mode
440
Signal Names and Descriptions
441
Table 204. Signal Properties
441
Memory Map and Registers Description
442
Table 205. DSPI Memory Map
442
Registers Description
443
Figure 207. DSPI Module Configuration Register (Dspix_Mcr)
444
Table 206. Dspix_Mcr Field Descriptions
444
Figure 208. DSPI Transfer Count Register (Dspix_Tcr)
447
Table 207. Dspix_Tcr Field Descriptions
447
Figure 209. DSPI Clock and Transfer Attributes Registers 0-7 (Dspix_Ctarn)
448
Table 208. Dspix_Ctarn Field Descriptions
448
Table 209. DSPI SCK Duty Cycle
451
Table 210. DSPI Transfer Frame Size
451
Table 211. DSPI PCS to SCK Delay Scaler
452
Table 212. DSPI after SCK Delay Scaler
452
Table 213. DSPI Delay after Transfer Scaler
452
Figure 210. DSPI Status Register (Dspix_Sr)
453
Table 214. DSPI Baud Rate Scaler
453
Table 215. Dspix_Sr Field Descriptions
453
Figure 211. DSPI DMA / Interrupt Request Select and Enable Register (Dspix_Rser)
455
Table 216. Dspix_Rser Field Descriptions
455
Figure 212. DSPI PUSH TX FIFO Register (Dspix_Pushr)
457
Table 217. Dspix_Pushr Field Descriptions
457
Figure 213. DSPI POP RX FIFO Register (Dspix_Popr)
459
Figure 214. DSPI Transmit FIFO Register 0-4 (Dspix_Txfrn)
459
Table 218. Dspix_Popr Field Descriptions
459
Figure 215. DSPI Receive FIFO Registers 0-4 (Dspix_Rxfrn)
460
Functional Description
460
Table 219. Dspix_Txfrn Field Descriptions
460
Table 220. Dspix_Rxfrn Field Description
460
Figure 216. SPI Serial Protocol Overview
461
Modes of Operation
461
Start and Stop of DSPI Transfers
462
Figure 217. DSPI Start and Stop State Diagram
463
Serial Peripheral Interface (SPI) Configuration
463
Table 221. State Transitions for Start and Stop of DSPI Transfers
463
DSPI Baud Rate and Clock Delay Generation
466
Figure 218. Communications Clock Prescalers and Scalers
466
Table 222. Baud Rate Computation Example
467
Table 223. CS to SCK Delay Computation Example
467
Table 224. after SCK Delay Computation Example
467
Figure 219. Peripheral Chip Select Strobe Timing
468
Table 225. Delay after Transfer Computation Example
468
Table 226. Peripheral Chip Select Strobe Assert Computation Example
469
Table 227. Peripheral Chip Select Strobe Negate Computation Example
469
Transfer Formats
469
Figure 220. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 0, FMSZ = 8)
470
Figure 221. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 1, FMSZ = 8)
471
Table 228. Delayed Master Sample Point
472
Figure 222. DSPI Modified Transfer Format (MTFE = 1, CPHA = 0, F SCK = F SYS / 4)
473
Figure 223. DSPI Modified Transfer Format (MTFE = 1, CPHA = 1, F SCK = F SYS / 4)
474
Figure 224. Example of Non-Continuous Format (CPHA = 1, CONT = 0)
474
Figure 225. Example of Continuous Transfer (CPHA = 1, CONT = 1)
475
Continuous Serial Communications Clock
476
Figure 226. Polarity Switching between Frames
476
Figure 227. Continuous SCK Timing Diagram (CONT = 0)
477
Figure 228. Continuous SCK Timing Diagram (CONT = 1)
477
Interrupts/Dma Requests
478
Table 229. Interrupt and DMA Request Conditions
478
Power Saving Features
479
Initialization and Application Information
480
Table 230. Baud Rate Values
481
Delay Settings
482
Table 231. Delay Values
482
Figure 229. TX FIFO Pointers and Counter
483
Introduction
485
Features Common to LIN and UART
486
Figure 230. LIN Topology Network
487
Figure 231. Linflex Block Diagram
487
Fractional Baud Rate Generation
487
Table 232. Error Calculation for Programmed Baud Rates
488
Figure 232. Linflex Operating Modes
489
Figure 233. Linflex in Loop Back Mode
490
Test Modes
490
Table 233. Linflex Memory Map
491
Figure 234. Linflex in Self Test Mode
491
Memory Map and Registers Description
491
Figure 235. LIN Control Register 1 (LINCR1)
492
Table 234. LINCR1 Field Descriptions
493
Table 235. Checksum Bits Configuration
494
Table 236. LIN Master Break Length Selection
494
Table 237. Operating Mode Selection
495
Figure 236. LIN Interrupt Enable Register (LINIER)
495
Table 238. LINIER Field Descriptions
496
Figure 237. LIN Status Register (LINSR)
497
Table 239. LINSR Field Descriptions
498
Table 240. LINESR Field Descriptions
500
Figure 238. LIN Error Status Register (LINESR)
500
Figure 239. UART Mode Control Register (UARTCR)
501
Table 241. UARTCR Field Descriptions
502
Table 242. UARTSR Field Descriptions
503
Figure 240. UART Mode Status Register (UARTSR)
503
Table 243. LINTCSR Field Descriptions
505
Figure 241. LIN Timeout Control Status Register (LINTCSR)
505
Table 244. LINOCR Field Descriptions
506
Figure 242. LIN Output Compare Register (LINOCR)
506
Figure 243. LIN Timeout Control Register (LINTOCR)
506
Table 245. LINTOCR Field Descriptions
507
Table 246. LINFBRR Field Descriptions
507
Figure 244. LIN Fractional Baud Rate Register (LINFBRR)
507
Table 247. LINIBRR Field Descriptions
508
Table 248. Integer Baud Rate Selection
508
Figure 245. LIN Integer Baud Rate Register (LINIBRR)
508
Table 249. LINCFR Field Descriptions
509
Figure 246. LIN Checksum Field Register (LINCFR)
509
Figure 247. LIN Control Register 2 (LINCR2)
509
Table 250. LINCR2 Field Descriptions
510
Table 251. BIDR Field Descriptions
511
Figure 248. Buffer Identifier Register (BIDR)
511
Table 252. BDRL Field Descriptions
512
Figure 249. Buffer Data Register LSB (BDRL)
512
Figure 250. Buffer Data Register MSB (BDRM)
512
Table 253. BDRM Field Descriptions
513
Table 254. IFER Field Descriptions
513
Figure 251. Identifier Filter Enable Register (IFER)
513
Table 255. IFMI Field Descriptions
514
Figure 252. Identifier Filter Match Index (IFMI)
514
Figure 253. Identifier Filter Mode Register (IFMR)
514
Table 256. IFMR Field Descriptions
515
Table 257. IFMR[IFM] Configuration
515
Table 258. Ifcr2N Field Descriptions
516
Figure 254. Identifier Filter Control Register (Ifcr2N)
516
Table 259. Ifcr2N + 1 Field Descriptions
517
Figure 255. Identifier Filter Control Register (Ifcr2N + 1)
517
Figure 256. UART Mode 8-Bit Data Frame
518
Figure 257. UART Mode 9-Bit Data Frame
518
Functional Description
518
Table 260. Message Buffer
519
LIN Mode
520
Table 261. Filter to Interrupt Vector Correlation
525
Figure 258. Filter Configuration-Register Organization
525
Figure 259. Identifier Match Index
526
Figure 260. LIN Synch Field Measurement
527
Bit Timeout Counter
528
Table 262. Linflex Interrupt Control
529
Figure 261. Header and Response Timeout
529
Interrupts
529
Figure 262. Flexcan Block Diagram
531
Introduction
531
Flexcan Module Features
532
Modes of Operation
533
Table 263. Flexcan Signals
534
External Signal Description
534
Table 264. Flexcan Module Memory Map
535
Table 265. Flexcan Register Reset Status
535
Table 266. Message Buffer MB0 Memory Mapping
536
Message Buffer Structure
536
Table 267. Message Buffer Structure Field Description
537
Figure 263. Message Buffer Structure
537
Table 268. Message Buffer Code for Rx Buffers
538
Table 269. Message Buffer Code for Tx Buffers
539
Table 270. MB0-MB31 Addresses
539
Rx FIFO Structure
540
Table 271. ID Table 0 - 7
541
Figure 264. Rx FIFO Structure
541
Table 272. Rx FIFO Structure Field Description
542
Registers Description
542
Table 273. MCR Field Descriptions
543
Figure 265. Module Configuration Register (MCR)
543
Table 274. IDAM Coding
546
Figure 266. Control Register (CTRL)
546
Table 275. CTRL Field Descriptions
547
Table 276. TIMER Field Descriptions
550
Figure 267. Free Running Timer (TIMER)
550
Figure 268. Rx Global Mask Register (RXGMASK)
550
Table 277. RXGMASK Field Description
551
Table 278. RX14MASK Field Description
551
Figure 269. Rx Buffer 14 Mask Register (RX14MASK)
551
Table 279. RX15MASK Field Description
552
Figure 270. Rx Buffer 15 Mask Register (RX15MASK)
552
Figure 271. Error Counter Register (ECR)
553
Table 280. Error and Status Register (ESR) Field Description
554
Figure 272. Error and Status Register (ESR)
554
Table 281. Fault Confinement State
556
Figure 273. Interrupt Masks 1 Register (IMASK1)
556
Table 282. IMASK1 Field Descriptions
557
Table 283. IFLAG1 Field Descriptions
557
Figure 274. Interrupt Flags 1 Register (IFLAG1)
557
Figure 275. Rx Individual Mask Registers (RXIMR0-RXIMR31)
558
Table 284. RXIMR0-RXIMR31 Field Descriptions
559
Table 285. RXIMR0-RXIMR31 Addresses
559
Functional Description
560
Arbitration Process
561
Matching Process
563
Data Coherence
564
Rx FIFO
566
CAN Protocol Related Features
567
Figure 276. CAN Engine Clocking Scheme
568
Figure 277. Segments Within the Bit Time
569
Table 286. Time Segment Syntax
570
Table 287. CAN Standard Compliant Bit Time Segment Settings
570
Figure 278. Arbitration, Match, and Move Time Windows
570
Table 288. Minimum Ratio between Peripheral Clock Frequency and CAN Bit Rate
571
Modes of Operation Details
571
Interrupts
572
Bus Interface
573
Flexcan Initialization Sequence
574
Overview
575
Figure 279. ADC Implementation Diagram
576
Device-Specific Implementation
576
Table 289. Configurations for Starting Normal Conversion
577
Functional Description
577
Figure 280. Normal Conversion Flow
578
Figure 281. Injected Sample/Conversion Sequence
579
Analog Clock Generator and Conversion Timings
580
Figure 282. Prescaler Simplified Block Diagram
581
ADC Sampling and Conversion Timing
581
Table 290. ADC Sampling and Conversion Timing at 5 V / 3.3 V for ADC0
582
Figure 283. Sampling and Conversion Timings
582
Table 291. Max/Min Adc_Clk Frequency and Related Configuration Settings at 5 V / 3.3 V for ADC0
583
ADC CTU (Cross Triggering Unit)
583
Table 292. Values of Wdgxh and Wdgxl Fields
584
Figure 284. Guarded Area
584
Programmable Analog Watchdog
584
Table 293. Example for Analog Watchdog Operation
585
DMA Functionality
585
Power-Down Mode
586
Table 294. ADC Digital Registers
587
Figure 285. Main Configuration Register (MCR)
588
Control Logic Registers
588
Table 295. MCR Field Descriptions
589
Table 296. MSR Field Descriptions
590
Figure 286. Main Status Register (MSR)
590
Figure 287. Interrupt Status Register (ISR)
591
Interrupt Registers
591
Table 297. ISR Field Descriptions
592
Table 298. IMR Field Descriptions
592
Figure 288. Interrupt Mask Register (IMR)
592
Table 299. WTISR Field Descriptions
593
Figure 289. Channel Interrupt Mask Register 0 (CIMR0)
593
Figure 290. Watchdog Threshold Interrupt Status Register (WTISR)
593
Table 300. WTIMR Field Descriptions
594
Figure 291. Watchdog Threshold Interrupt Mask Register (WTIMR)
594
Table 301. DMAE Field Descriptions
595
Figure 292. DMA Enable (DMAE) Register
595
DMA Registers
595
Table 302. Dmarx Field Descriptions
596
Figure 293. DMA Channel Select Register 0 (DMAR0)
596
Table 303. Trcx Field Descriptions
597
Figure 294. Threshold Control Register (Trcx, X = [0
597
Threshold Registers
597
Table 304. Thrhlrx Field Descriptions
598
Figure 295. Threshold Register (THRHLR[0:3])
598
Table 305. CTR Field Descriptions
599
Figure 296. Conversion Timing Registers CTR[0]
599
Table 306. NCMR Field Descriptions
600
Table 307. JCMR Field Descriptions
600
Figure 297. Normal Conversion Mask Register 0 (NCMR0)
600
Figure 298. Injected Conversion Mask Register 0 (JCMR0)
600
Table 308. PDEDR Field Descriptions
601
Figure 299. Power-Down Exit Delay Register (PDEDR)
601
Delay Registers
601
Table 309. CDR Field Descriptions
602
Figure 300. Channel Data Registers (CDR[0
602
Introduction
603
Figure 301. Cross Triggering Unit Diagram
604
Functional Description
604
Figure 302. TGS in Triggered Mode
605
Trigger Generator Subunit (TGS)
605
Figure 303. Example Timing for TGS in Triggered Mode
606
TGS in Sequential Mode
606
Figure 304. TGS in Sequential Mode
607
Figure 305. Example Timing for TGS in Sequential Mode
607
TGS Counter
607
Figure 306. TGS Counter Cases
608
Scheduler Subunit (SU)
608
ADC Commands List
610
Figure 307. Scheduler Subunit
610
Table 310. ADC Commands Translation
611
ADC Results
612
Reload Mechanism
613
Figure 308. Reload Error Scenario
614
Power Safety Mode
614
Interrupts and DMA Requests
615
CTU Interrupt/Dma Requests
616
Table 311. CTU Interrupts
616
Table 312. CTU Memory Map
617
Table 313. TGS Registers
620
Table 314. SU Registers
620
Table 315. CTU Registers
620
Figure 309. Trigger Generator Sub-Unit Input Selection Register (TGSISR)
621
Table 316. FIFO Registers
621
Table 317. TGSISR Field Descriptions
622
Figure 310. Trigger Generator Sub-Unit Control Register (TGSCR)
624
Figure 311. Trigger X Compare Register (Txcr, X = 0
624
Table 318. TGSCR Field Descriptions
624
Figure 312. TGS Counter Compare Register (TGSCCR)
625
Figure 313. TGS Counter Reload Register (TGSCRR)
625
Table 319. Txcr Field Descriptions
625
Table 320. TGSCCR Field Format
625
Table 321. TGSCRR Field Descriptions
625
Figure 314. Commands List Control Register 1 (CLCR1)
626
Figure 315. Commands List Control Register 2 (CLCR2)
626
Table 322. CLCR1 Field Descriptions
626
Table 323. CLCR2 Field Descriptions
626
Figure 316. Trigger Handler Control Register 1 (THCR1)
627
Table 324. THCR1 Field Descriptions
627
Figure 317. Trigger Handler Control Register 2 (THCR2)
629
Table 325. THCR2 Field Descriptions
629
Commands List Register X (X = 1,...,24) (Clrx)
631
Figure 318. Commands List Register X (X = 1
631
Figure 319. Commands List Register X (X = 1
631
Table 326. Clrx (CMS = 0) Field Descriptions
631
Figure 320. FIFO DMA Control Register (FDCR)
632
Table 327. Clrx (CMS = 1) Field Descriptions
632
Table 328. FDCR Field Descriptions
632
Figure 321. FIFO Control Register (FCR)
633
Table 329. FCR Field Descriptions
633
Figure 322. FIFO Threshold Register (FTH)
634
Table 330. FTH Field Descriptions
634
Figure 323. FIFO Status Register (FST)
635
Table 331. FST Field Descriptions
635
FIFO Right Aligned Data X (X = 0,...,3) (Frx)
636
Figure 324. FIFO Right Aligned Data X (X = 0
636
FIFO Signed Left Aligned Data X (X = 0,...,3) (Flx)
637
Figure 325. FIFO Signed Left Aligned Data X (X = 0
637
Figure 326. Cross Triggering Unit Error Flag Register (CTUEFR)
637
Table 332. Frx Field Descriptions
637
Table 333. Flx Field Descriptions
637
Figure 327. Cross Triggering Unit Interrupt Flag Register (CTUIFR)
638
Table 334. CTUEFR Field Descriptions
638
Figure 328. Cross Triggering Unit Interrupt/Dma Register (CTUIR)
639
Table 335. CTUIFR Field Descriptions
639
Figure 329. Control on Time Register (COTR)
640
Table 336. CTUIR Field Descriptions
640
Figure 330. Cross Triggering Unit Control Register (CTUCR)
641
Table 337. COTR Field Descriptions
641
Table 338. CTUCR Field Descriptions
641
Figure 331. Cross Triggering Unit Digital Filter (CTUDF)
642
Figure 332. Cross Triggering Unit Power Control Register (CTUPCR)
642
Table 339. CTUDF Field Descriptions
642
Table 340. CTUPCR Field Descriptions
642
Overview
643
Table 341. Modes When PWM Operation Is Restricted
644
Figure 333. PWM Block Diagram
645
Block Diagrams
645
Figure 334. PWM Submodule Block Diagram
646
External Signal Descriptions
647
Memory Map and Registers
648
Table 342. Flexpwm Memory Map
648
Register Descriptions
650
Figure 335. Counter Register (CNT)
651
Figure 336. Initial Count Register (INIT)
651
Submodule Registers
651
Figure 337. Control 2 Register (CTRL2)
652
Table 343. CTRL2 Field Descriptions
652
Figure 338. Control 1 Register (CTRL1)
654
Table 344. CTRL1 Field Descriptions
654
Table 345. PWM Reload Frequency
655
Figure 339. Value Register 0 (VAL0)
656
Table 346. PWM Prescaler
656
Figure 340. Value Register 1 (VAL1)
657
Figure 341. Value Register 2 (VAL2)
657
Figure 342. Value Register 3 (VAL3)
658
Figure 343. Value Register 4 (VAL4)
658
Figure 344. Value Register 5 (VAL5)
659
Figure 345. Output Control Register (OCTRL)
659
Table 347. OCTRL Field Descriptions
659
Figure 346. Status Register (STS)
660
Figure 347. Interrupt Enable Register (INTEN)
661
Table 348. STS Field Descriptions
661
Figure 348. DMA Enable Register (DMAEN)
662
Table 349. INTEN Field Descriptions
662
Table 350. DMAEN Field Descriptions
662
Figure 349. Output Trigger Control Register (TCTRL)
663
Table 351. TCTRL Field Descriptions
663
Figure 350. Fault Disable Mapping Register (DISMAP)
664
Table 352. DISMAP Field Descriptions
664
Configuration Registers
665
Figure 351. Deadtime Count Register 0 (DTCNT0)
665
Figure 352. Deadtime Count Register 1 (DTCNT1)
665
Figure 353. Output Enable Register (OUTEN)
665
Figure 354. Mask Register (MASK)
666
Table 353. OUTEN Field Descriptions
666
Table 354. MASK Field Descriptions
666
Figure 355. Software Controlled Output Register (SWCOUT)
667
Table 355. SWCOUT Field Descriptions
667
Figure 356. Deadtime Source Select Register (DTSRCSEL)
668
Table 356. DTSRCSEL Field Descriptions
669
Figure 357. Master Control Register (MCTRL)
670
Fault Channel Registers
671
Figure 358. Fault Control Register (FCTRL)
671
Table 357. MCTRL Field Descriptions
671
Figure 359. Fault Status Register (FSTS)
672
Table 358. FCTRL Field Descriptions
672
Figure 360. Fault Filter Register (FFILT)
673
Table 359. FSTS Field Descriptions
673
Table 360. FFILT Field Descriptions
673
Figure 361. Center-Aligned Example
675
Functional Description
675
Edge-Aligned Pwms
676
Figure 362. Edge-Aligned Example (INIT = VAL2 = VAL4)
676
Figure 363. Phase-Shifted Outputs Example
677
Double Switching Pwms
678
Figure 364. Phase-Shifted Pwms Applied to a Transformer Primary
678
ADC Triggering
679
Figure 365. Double Switching Output Example
679
Figure 366. Multiple Output Trigger Generation in Hardware
680
Figure 367. Multiple Output Triggers over Several PWM Cycles
681
Synchronous Switching of Multiple Outputs
681
Figure 368. Sensorless BLDC Commutation Using the Force out Function
682
Functional Details
682
Figure 369. Clocking Block Diagram for each PWM Submodule
683
Counter Synchronization
684
Figure 370. Register Reload Logic
684
Figure 371. Submodule Timer Synchronization
684
PWM Generation
685
Figure 372. PWM Generation Hardware
686
Output Compare Capabilities
687
Figure 373. Force out Logic
688
Independent or Complementary Channel Operation
688
Deadtime Insertion Logic
689
Figure 374. Complementary Channel Pair
689
Figure 375. Typical 3-Phase AC Motor Drive
689
Figure 376. Deadtime Insertion and Fine Control Logic
690
Figure 377. Deadtime Insertion
691
Top/Bottom Correction
691
Figure 378. Deadtime Distortion
692
Figure 379. Current-Status Sense Scheme for Deadtime Correction
693
Manual Correction
693
Figure 380. Output Voltage Waveforms
694
Output Logic
694
Fault Protection
695
Figure 381. Output Logic Section
695
Fault Pin Filter
696
Figure 382. Fault Decoder for PWMA
696
Table 361. Fault Mapping
696
Figure 383. Automatic Fault Clearing
697
Fault Testing
698
Figure 384. Manual Fault Clearing (FSAFE = 0)
698
Figure 385. Manual Fault Clearing (FSAFE = 1)
698
Figure 386. Full Cycle Reload Frequency Change
699
Figure 387. Half Cycle Reload Frequency Change
699
Load Frequency
699
Figure 388. Full and Half Cycle Reload Frequency Change
700
Figure 389. PWMF Reload Interrupt Request
700
Reload Flag
700
Table 362. Interrupt Summary
701
Clocks
701
Table 363. DMA Summary
702
Etimer
703
Features
704
Figure 390. Etimer Block Diagram
705
Module Block Diagram
705
Figure 391. Etimer Channel Block Diagram
706
Table 364. Etimer Memory Map
707
Figure 392. Compare Register 1 (COMP1)
710
Timer Channel Registers
710
Figure 393. Compare Register 2 (COMP2)
711
Figure 394. Capture Register 1 (CAPT1)
711
Table 365. COMP1 Field Descriptions
711
Table 366. COMP2 Field Descriptions
711
Figure 395. Capture Register 2 (CAPT2)
712
Figure 396. Load Register (LOAD)
712
Table 367. CAPT1 Field Descriptions
712
Table 368. CAPT2 Field Descriptions
712
Figure 397. Hold Register (HOLD)
713
Figure 398. Counter Register (CNTR)
713
Table 369. LOAD Field Descriptions
713
Table 370. HOLD Field Descriptions
713
Figure 399. Control Register 1 (CTRL1)
714
Table 371. CNTR Field Descriptions
714
Table 372. CTRL1 Field Descriptions
714
Table 373. Count Source Values
715
Figure 400. Control Register 2 (CTRL2)
716
Table 374. CTRL2 Field Descriptions
716
Figure 401. Control Register 3 (CTRL3)
718
Figure 402. Status Register (STS)
719
Table 375. CTRL3 Field Descriptions
719
Table 376. STS Field Descriptions
720
Figure 403. Interrupt and DMA Enable Register (INTDMA)
721
Table 377. INTDMA Field Descriptions
721
Figure 404. Comparator Load 1 (CMPLD1)
722
Figure 405. Comparator Load 2 (CMPLD2)
722
Table 378. CMPLD1 Field Descriptions
722
Figure 406. Compare and Capture Control Register (CCCTRL)
723
Table 379. CMPLD2 Field Descriptions
723
Table 380. CCCTRL Field Descriptions
723
Figure 407. Input Filter Register (FILT)
725
Table 381. FILT Field Descriptions
725
Watchdog Timer Registers
725
Configuration Registers
726
Figure 408. Watchdog Time-Out Low Word Register (WDTOL)
726
Figure 409. Watchdog Time-Out High Word Register (WDTOH)
726
Figure 410. Channel Enable Register (ENBL)
726
Table 382. WDTOL, WDTOH Field Descriptions
726
Figure 411. DMA Request 0 Select Register (DREQ0)
727
Figure 412. DMA Request 1 Select Register (DREQ1)
727
Table 383. ENBL Field Descriptions
727
Table 384. Dreqn Field Descriptions
728
Functional Description
729
Figure 413. Quadrature Incremental Position Encoder
730
Figure 414. Triggered Count Mode (Length = 1)
731
Figure 415. One-Shot Mode (Length = 1)
731
Figure 416. Pulse Output Mode
732
Figure 417. Variable PWM Waveform
733
Other Features
734
Clocks
735
Table 385. Interrupt Summary
736
Table 386. DMA Summary
736
Interrupts
736
Figure 418. Register Protection Module Block Diagram
737
Functional Safety
737
Figure 419. Register Protection Memory Diagram
738
Features
738
Table 387. Register Protection Memory Map
739
Figure 420. Soft Lock Bit Register (Slbrn)
740
Table 388. Slbrn Field Descriptions
740
Figure 421. Global Configuration Register (GCR)
741
Table 389. Soft Lock Bits Vs. Protected Address
741
Table 390. GCR Field Descriptions
741
Figure 422. Change Lock Settings Directly Via Area #4
742
Functional Description
742
Figure 423. Change Lock Settings for 16-Bit Protected Addresses
743
Figure 424. Change Lock Settings for 32-Bit Protected Addresses
743
Figure 425. Change Lock Settings for Mixed Protection
744
Figure 426. Enable Locking Via Mirror Module Space (Area #3)
744
Figure 427. Enable Locking for Protected and Unprotected Addresses
744
Reset
745
Features
746
Figure 428. SWT Control Register (SWT_CR)
747
Table 391. SWT Memory Map
747
Table 392. SWT_CR Field Descriptions
747
Figure 429. SWT Interrupt Register (SWT_IR)
749
Figure 430. SWT Time-Out Register (SWT_TO)
749
Table 393. SWT_IR Field Descriptions
749
Figure 431. SWT Window Register (SWT_WN)
750
Table 394. SWT_TO Field Descriptions
750
Table 395. SWT_WN Field Descriptions
750
Figure 432. SWT Service Register (SWT_SR)
751
Figure 433. SWT Counter Output Register (SWT_CO)
751
Table 396. SWT_SR Field Descriptions
751
Figure 434. SWT Service Register (SWT_SR)
752
Functional Description
752
Table 397. SWT_CO Field Descriptions
752
Table 398. SWT_SR Field Descriptions
752
Fault Collection Unit (FCU)
754
Figure 435. Fault Collection Unit (FCU) Block Diagram
755
Figure 436. FCU Fault Handling
756
Features
757
Table 399. FCU Memory Map
758
Table 400. Register Summary
758
Figure 437. Module Configuration Register (FCU_MCR)
760
Register Descriptions
760
Table 401. FCU_MCR Field Description
761
Figure 438. Fault Flag Register (FCU_FFR)
762
Table 402. FCU_FFR Field Descriptions
762
Table 403. Hardware/Software Fault Description
762
Figure 439. Frozen Fault Flag Register (FCU_FFFR)
763
Figure 440. Fake Fault Generation Register (FCU_FFGR)
764
Table 404. FCU_FFFR Field Descriptions
764
Table 405. FCU_FFGR Field Description
764
Figure 441. Fault Enable Register (FCU_FER)
765
Table 406. FCU_FER Field Descriptions
765
Figure 442. Key Register (FCU_KR)
766
Figure 443. Timeout Register (FCU_TR)
766
Table 407. FCU_TR Field Descriptions
766
Figure 444. Timeout Enable Register (FCU_TER)
767
Figure 445. Module State Register (FCU_MSR)
767
Table 408. FCU_TER Field Descriptions
767
Figure 446. MC State Register (FCU_MCSR)
768
Table 409. FCU_MSR Field Descriptions
768
Table 410. FCU_MCSR Field Description
769
Figure 447. Frozen MC State Register (FCU_FMCSR)
770
Table 411. FCU_FMCSR Field Description
770
Figure 448. Functional Block Diagram
771
Functional Description
771
Figure 449. Finite State Machine
772
Output Generation Protocol
773
Table 412. Dual-Rail Coding
773
Figure 450. Dual Rail Coding Example
774
Figure 451. Time Switching Protocol Example
774
Figure 452. Bi-Stable Coding Example
775
Table 413. Bi-Stable Coding
775
Table 414. WKPU Memory Map
776
Wakeup Unit (WKPU)
776
Table 415. NSR Field Descriptions
777
Figure 453. NMI Status Flag Register (NSR)
777
Registers Description
777
Figure 454. NMI Configuration Register (NCR)
778
Table 416. NCR Field Descriptions
778
Figure 455. NMI Pad Diagram
779
Functional Description
779
Figure 456. PIT Block Diagram
781
Periodic Interrupt Timer (PIT)
781
Signal Description
782
Table 417. PIT Memory Map
782
Figure 457. PIT Module Control Register (PITMCR)
783
Registers Description
783
Table 418. PITMCR Field Descriptions
783
Figure 458. Timer Load Value Register N (Ldvaln)
784
Table 419. Ldvaln Field Descriptions
784
Figure 459. Current Timer Value Register N (Cvaln)
785
Table 420. Cvaln Field Descriptions
785
Figure 460. Timer Control Register N (Tctrln)
786
Table 421. Tctrln Field Descriptions
786
Figure 461. Timer Flag Register N (Tflgn)
787
Functional Description
787
Table 422. Tflgn Field Descriptions
787
Figure 462. Stopping and Starting a Timer
788
Figure 463. Modifying Running Timer Period
788
Figure 464. Dynamically Setting a New Load Value
788
Interrupts
789
System Timer Module (STM)
790
Table 423. STM Memory Map
790
Figure 465. STM Control Register (STM_CR)
791
Registers Description
791
Figure 466. STM Count Register (STM_CNT)
792
Table 424. STM_CR Field Descriptions
792
Table 425. STM_CNT Field Descriptions
792
Figure 467. STM Channel Control Register (Stm_Ccrn)
793
Figure 468. STM Channel Interrupt Register (Stm_Cirn)
793
Table 426. Stm_Ccrn Field Descriptions
793
Figure 469. STM Channel Compare Register (Stm_Cmpn)
794
Table 427. Stm_Cirn Field Descriptions
794
Table 428. Stm_Cmpn Field Descriptions
794
Functional Description
795
Cyclic Redundancy Check (CRC)
796
Figure 470. CRC Top Level Diagram
797
IPS Bus Interface
797
Figure 471. CRC-CCITT Engine Concept Scheme
798
Figure 472. CRC Computation Flow
799
Memory Map and Registers Description
799
Table 429. CRC Memory Map
799
Figure 473. CRC Configuration Register (CRC_CFG)
800
Table 430. CRC_CFG Field Descriptions
800
Figure 474. CRC Input Register (CRC_INP)
801
Table 431. CRC_INP Field Descriptions
801
Figure 475. CRC Current Status Register (CRC_CSTAT)
802
Figure 476. CRC Output Register (CRC_OUTP)
802
Table 432. CRC_CSTAT Field Descriptions
802
Table 433. CRC_OUTP Field Descriptions
803
Use Cases and Limitations
803
Figure 477. DMA-CRC Transmission Sequence
804
Figure 478. DMA-CRC Reception Sequence
805
Table 434. BAM Memory Organization
806
Boot Assist Module (BAM)
806
Figure 479. Boot Mode Selection
807
Functional Description
807
Table 435. Hardware Configuration to Select Boot Mode
808
Table 436. SPC560P40/34 Boot Pins
808
Figure 480. Reset Configuration Half Word (RCHW)
809
Table 437. RCHW Field Descriptions
809
Figure 481. SPC560P40/34 Flash Partitioning and RCHW Search
810
Single Chip Boot Mode
810
Table 438. Flash Boot Sector
810
Boot through BAM
811
Figure 482. BAM Logic Flow
812
Table 439. Fields of SSCM STATUS Register Used by BAM
813
Table 440. Serial Boot Mode Without Autobaud-Baud Rates
813
Figure 483. Password Check Flow
816
Boot from Uart—Autobaud Disabled
817
Figure 484. Start Address, VLE Bit and Download Size in Bytes
817
Bootstrap with Flexcan—Autobaud Disabled
818
Figure 485. Linflex Bit Timing in UART Mode
818
Table 441. UART Boot Mode Download Protocol (Autobaud Disabled)
818
Figure 486. Flexcan Bit Timing
819
Table 442. Flexcan Boot Mode Download Protocol (Autobaud Disabled)
819
Table 443. System Clock Frequency Related to External Clock Frequency
820
Figure 487. BAM Autoscan Code Flow
822
Figure 488. Baud Measurement on UART Boot
822
Figure 489. BAM Rate Measurement Flow During UART Boot
823
Table 444. Maximum and Minimum Recommended Baud Rates
824
Figure 490. Baud Rate Deviation between Host and SPC560P40/34
825
Figure 491. Bit Time Measure
826
Figure 492. BAM Rate Measurement Flow During Flexcan Boot
827
Table 445. Prescaler/Divider and Time Base Values
828
Table 446. Flexcan Standard Compliant Bit Timing Segment Settings
829
Table 447. Lookup Table for Flexcan Bit Timings
829
Table 448. PRESDIV + 1 = 1
829
Table 449. PRESDIV + 1 > 1 (YY = PRESDIV)
830
Interrupt
831
Table 450. Examples of Legal and Illegal Passwords
832
Table 451. Censorship Configuration and Truth Table
833
Figure 493. Censorship Control in Flash Memory Boot Mode
834
Figure 494. Censorship Control in Serial Boot Mode
835
Voltage Regulators and Power Supplies
836
VREG Digital Interface
837
Table 452. VREG_CTL Field Descriptions
838
Figure 495. Voltage Regulator Control Register (VREG_CTL)
838
Registers Description
838
Table 453. VREG_STATUS Field Descriptions
839
Figure 496. Voltage Regulator Status Register (VREG_STATUS)
839
Power Supply Strategy
839
Figure 497. JTAG Controller Block Diagram
841
IEEE 1149.1 Test Access Port Controller (JTAGC)
841
Features
842
Table 454. JTAG Signal Properties
843
External Signal Description
843
Figure 498. 5-Bit Instruction Register
844
Figure 499. Device Identification Register
844
Boundary Scan Register
845
Figure 500. Shifting Data through a Register
845
Table 455. Device Identification Register Field Descriptions
845
TAP Controller State Machine
846
Figure 501. IEEE 1149.1-2001 TAP Controller Finite State Machine
847
JTAGC Instructions
848
Table 456. JTAG Instructions
848
Boundary Scan
850
E200Z0 Once Controller Functional Description
851
Figure 502. E200Z0 Once Block Diagram
851
Figure 503. Once Command Register (OCMD)
852
Table 457. E200Z0 Once Register Addressing
852
Initialization/Application Information
853
Nexus Development Interface (NDI)
854
Figure 504. NDI Functional Block Diagram
855
Modes of Operation
856
Memory Map and Registers Description
857
Debug Support Overview
858
Hardware Debug Facilities
859
Figure 505. E200Z0H Debug Resources
861
Software Debug Events and Exceptions
861
Instruction Address Compare Event
862
Data Address Compare Event
863
Table 458. DAC Events and Resultant Updates
864
Linked Instruction Address and Data Address Compare Event
865
Trap Debug Event
866
Critical Interrupt Taken Debug Event
867
Unconditional Debug Event
868
Figure 506. DVC1, DVC2 Registers
869
Debug Control and Status Registers
869
Table 459. DBCR0 Bit Definitions
870
Figure 507. DBCR0 Register
870
Figure 508. DBCR1 Register
872
Table 460. DBCR1 Bit Definitions
873
Table 461. DBCR2 Bit Definitions
875
Figure 509. DBCR2 Register
875
Table 462. DBCR4 Bit Definitions
879
Figure 510. DBCR4 Register
879
Figure 511. DBSR Register
880
Table 463. DBSR Bit Definitions
881
Debug External Resource Control Register (DBERC0)
882
Figure 512. DBERC0 Register
883
Table 464. DBERC0 Bit Definitions
884
Table 465. DBERC0 Resource Control
886
External Debug Support
888
Figure 513. Once TAP Controller and Registers
889
Figure 514. IEEE 1149.1-2001 TAP Controller State Machine
890
Jtag/Once Pins
891
Table 466. Jtag/Once Primary Interface Signals
891
Once Interface Signals
892
E200Z0H Once Controller and Serial Interface
893
Figure 515. E200Z0H Once Controller and Serial Interface
894
Figure 516. Once Status Register
894
Table 467. Once Status Register Bit Definitions
895
Figure 517. Once Command Register
896
Table 468. Once Command Register Bit Definitions
896
Table 469. E200Z0H Once Register Addressing
897
Figure 518. Once Control Register
899
Table 470. Once Control Register Bit Definitions
899
Access to Debug Resources
901
Table 471. Once Register Access Requirements
902
Methods of Entering Debug Mode
903
CPU Status and Control Scan Chain Register (CPUSCR)
904
Figure 519. CPU Scan Chain Register (CPUSCR)
905
Figure 520. Control State Register (CTL)
906
Table 472. Watchpoint Output Signal Assignments
910
Watchpoint Support
910
Basic Steps for Enabling, Using, and Exiting External Debug Mode
911
Functional Description
912
Table 473. JTAGC Instruction Opcodes to Enable Nexus Clients
913
Table 474. Nexus Client JTAG Instructions
913
Debug Mode Control
913
Table 475. Registers under Protection
914
Table 476. Revision History
925
Document Revision History
925
Figure 57. Peripheral Status Register 0 (ME_PS0)
933
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