Mode Entry Module (MC_ME) RM0046
176/936 Doc ID 16912 Rev 5
Peripheral Clocks Enable
Based on the current and target device modes, the peripheral configuration registers
ME_RUN_PC0…7, ME_LP_PC0…7, and the peripheral control registers ME_PCTL0…143,
the MC_ME enables the clocks for selected modules as required. This step is executed only
after the process is completed.
Processor and Memory Clock Enable
If the mode transition is from any of the low-power modes HALT0 or STOP0 to RUN0…3,
the clocks to the processor and system memory are enabled. The process of enabling these
clocks is executed only after the Flash Modules Switch-On process is completed.
Processor Low-Power Mode Exit
If the mode transition is from any of the low-power modes HALT0 orSTOP0 to RUN0…3, the
MC_ME requests the processor to exit from its halted or stopped state. This step is
executed only after the Processor and Memory Clock Enable process is completed.
System Clock Switching
Based on the SYSCLK bit field of the ME_<current mode>_MC and
ME_<target mode>_MC registers, if the target and current system clock configurations
differ, the following method is implemented for clock switching.
● The target clock configuration for the 16 MHz int. RC osc. takes effect only after the
S_16 MHz_IRC bit of the ME_GS register is set by hardware (i.e., the 16 MHz internal
RC oscillator has stabilized).
● The target clock configuration for the 4 MHz crystal osc. takes effect only after the
S_XOSC0 bit of the ME_GS register is set by hardware (i.e the 4 MHz crystal oscillator
has stabilized).
● The target clock configuration for the system PLL takes effect only after the S_PLL0 bit
of the ME_GS register is set by hardware (i.e., the system PLL has stabilized).
● If the clock is to be disabled, the SYSCLK bit field should be programmed with “1111”.
This is possible only in theTEST mode.
The current system clock configuration can be observed by reading the S_SYSCLK bit field
of the ME_GS register, which is updated after every system clock switching. Until the target
clock is available, the system uses the previous clock configuration.
System clock switching starts only after
● the Clock Sources Switch-On process has completed if the target system clock source
is one of the following:
– the 16 MHz internal RC oscillator
– the system PLL
● the Peripheral Clocks Disable process has completed in order not to change the
system clock frequency before peripherals close their internal activities
An overview of system clock source selection possibilities for each mode is shown in
Table 5 2. A ‘
’ indicates that a given clock source is selectable for a given mode.
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