RM0046 Mode Entry Module (MC_ME)
Doc ID 16912 Rev 5 175/936
The clocks to the processor and system memory are unaffected while transitioning between
software running modes such as DRUN, RUN0…3, and SAFE.
Warning: Clocks to the whole device including the processor and
system memory can be disabled in TEST mode.
Clock Sources Switch-On
On completion of the Processor Low-Power Mode Entry step, the MC_ME switches on all
clock sources based on the <clock source>ON bits of the ME_<current mode>_MC and
ME_<target mode>_MC registers. The following clock sources are switched on at this step:
● the 16 MHz internal RC oscillator
● the 4 MHz crystal oscillator
● the system PLL
The clock sources that are required by the target mode are switched on. The duration
required for the output clocks to be stable depends on the type of source, and all further
steps of mode transition depending on one or more of these clocks waits for the stable
status of the respective clocks. The availability status of these clocks is updated in the
S_<clock source> bits of ME_GS register.
The clock sources which need to be switched off are unaffected during this process in order
to not disturb the system clock which might require one of these clocks before switching to a
different target clock.
Flash Modules Switch-On
On completion of the step, if one or more of the flashes needs to be switched to normal
mode from its low-power or power-down mode based on the CFLAON and DFLAON bit
fields of the ME_<current mode>_MC and ME_<target mode>_MC registers, the MC_ME
requests the flash to exit from its low-power/power-down mode. When the flashes are
available for access, the S_CFLA and S_DFLA bit fields of the ME_GS register are updated
to “11” by hardware.
Warning: It is illegal to switch the flashes from low-power mode to
power-down mode and from power-down mode to low-power
mode. The MC_ME, however, does not prevent this nor does
it flag it.
Pad Outputs-On
On completion of the step, if the PDO bit of the ME_<target mode>_MC register is cleared,
then
● all pad outputs are enabled to return to their previous state
● the I/O pads power sequence driver is switched on
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