ST SPC560P34 - Page 174

Mode Entry Module (MC_ME) RM0046
174/936 Doc ID 16912 Rev 5
Peripheral Clocks Disable
On completion of the Target Mode Request step, the MC_ME requests each peripheral to
enter its stop mode when:
● the peripheral is configured to be disabled via the target mode, the peripheral
configuration registers ME_RUN_PC0…7 and ME_LP_PC0…7, and the peripheral
control registers ME_PCTL0…143
Warning: The MC_ME does not automatically request peripherals to
enter their stop modes if the power domains in which they
are residing are to be turned off due to a mode change.
Therefore, it is software’s responsibility to ensure that those
peripherals that are to be powered down are configured in
the MC_ME to be frozen.
Each peripheral acknowledges its stop mode request after closing its internal activity. The
MC_ME then disables the corresponding clock(s) to this peripheral.
In the case of a SAFE mode transition request, the MC_ME does not wait for the peripherals
to acknowledge the stop requests. The SAFE mode clock gating configuration is applied
immediately regardless of the status of the peripherals’ stop acknowledges.
Please refer to Section 6.4.6, “Peripheral Clock Gating“ for more details.
Each peripheral that may block or disrupt a communication bus to which it is connected
ensures that these outputs are forced to a safe or recessive state when the device enters
the SAFE mode.
Processor Low-Power Mode Entry
If, on completion of the Peripheral Clocks Disable step, the mode transition is to the HALT0
mode, the MC_ME requests the processor to enter its halted state. The processor
acknowledges its halt state request after completing all outstanding bus transactions.
If, on completion of the Peripheral Clocks Disable step, the mode transition is to the STOP0
mode, the MC_ME requests the processor to enter its stopped state. The processor
acknowledges its stop state request after completing all outstanding bus transactions.
Processor and System Memory Clock Disable
If, on completion of the Processor Low-Power Mode Entry step, the mode transition is to the
HALT0 or STOP0 mode and the processor is in its appropriate halted or stopped state, the
MC_ME disables the processor and system memory clocks to achieve further power saving.
PDO
 
off off on off off off off
Table 51. MC_ME Resource Control Overview (continued)
Resource
Mode
RESET TEST SAFE DRUN RUN0…3 HALT0 STOP0