ST SPC560P34 - Page 871

RM0046 Nexus Development Interface (NDI)
Doc ID 16912 Rev 5 871/936
2:3 RST
Reset Control
00 – No function
01 – Reserved
10 – p_resetout_b pin asserted by Debug Reset Control. Allows external device to initiate
processor reset.
11 – Reserved
4ICMP
Instruction Complete Debug Event Enable
0 – ICMP debug events are disabled
1 – ICMP debug events are enabled
5BRT
Branch Taken Debug Event Enable
0 – BRT debug events are disabled
1 – BRT debug events are enabled
6IRPT
Interrupt Taken Debug Event Enable
0 – IRPT debug events are disabled
1 – IRPT debug events are enabled
7TRAP
Trap Taken Debug Event Enable
0 – TRAP debug events are disabled
1 – TRAP debug events are enabled
8IAC1
Instruction Address Compare 1 Debug Event Enable
0 – IAC1 debug events are disabled
1 – IAC1 debug events are enabled
9IAC2
Instruction Address Compare 2 Debug Event Enable
0 – IAC2 debug events are disabled
1 – IAC2 debug events are enabled
10 IAC3
Instruction Address Compare 3 Debug Event Enable
0 – IAC3 debug events are disabled
1 – IAC3 debug events are enabled
11 IAC4
Instruction Address Compare 4 Debug Event Enable
0 – IAC4 debug events are disabled
1 – IAC4 debug events are enabled
12:13 DAC1
Data Address Compare 1 Debug Event Enable
00 – DAC1 debug events are disabled
01 – DAC1 debug events are enabled only for store-type data storage accesses
10 – DAC1 debug events are enabled only for load-type data storage accesses
11 – DAC1 debug events are enabled for load-type or store-type data storage accesses
14:15 DAC2
Data Address Compare 2 Debug Event Enable
00 – DAC2 debug events are disabled
01 – DAC2 debug events are enabled only for store-type data storage accesses
10 – DAC2 debug events are enabled only for load-type data storage accesses
11 – DAC2 debug events are enabled for load-type or store-type data storage accesses
Table 459. DBCR0 Bit Definitions (continued)
Bit(s) Name Description