RM0046 Enhanced Direct Memory Access (eDMA)
Doc ID 16912 Rev 5 405/936
242–247
0x1C [18:23]
MAJOR.LINKC
H
[0:5]
Link channel number. If channel-to-channel linking on major loop complete is
disabled (TCD.MAJOR.E_LINK = 0) then:
– No channel-to-channel linking (or chaining) is performed after the outer major
loop counter is exhausted.
Otherwise
– After the major loop counter is exhausted, the eDMA engine initiates a channel
service request at the channel defined by MAJOR.LINKCH[0:5] by setting that
channel’s TCD.START bit.
248
0x1C [24]
DONE
Channel done. This flag indicates the eDMA has completed the outer major loop. It
is set by the eDMA engine as the CITER count reaches zero; it is cleared by
software or hardware when the channel is activated (when the channel has begun
to be processed by the eDMA engine, not when the first data transfer occurs).
This bit must be cleared to write the MAJOR.E_LINK or E_SG bits.
249
0x1C [25]
ACTIVE
Channel active. This flag signals the channel is currently in execution. It is set
when channel service begins, and is cleared by the eDMA engine as the inner
minor loop completes or if any error condition is detected.
250
0x1C [26]
MAJOR.E_LINK
Enable channel-to-channel linking on major loop completion. As the channel
completes the outer major loop, this flag enables the linking to another channel,
defined by MAJOR.LINKCH[0:5]. The link target channel initiates a channel
service request via an internal mechanism that sets the TCD.START bit of the
specified channel.
NOTE: To support the dynamic linking coherency model, this field is forced to zero
when written to while the TCD.DONE bit is set.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.
251
0x1C [27]
E_SG
Enable scatter/gather processing. As the channel completes the outer major loop,
this flag enables scatter/gather processing in the current channel. If enabled, the
eDMA engine uses DLAST_SGA as a memory pointer to a 0-modulo-32 address
containing a 32-byte data structure that is loaded as the transfer control descriptor
into the local memory.
NOTE: To support the dynamic scatter/gather coherency model, this field is forced
to zero when written to while the TCD.DONE bit is set.
0 The current channel’s TCD is “normal” format.
1 The current channel’s TCD specifies a scatter gather format. The DLAST_SGA
field provides a memory pointer to the next TCD to be loaded into this channel
after the outer major loop completes its execution.
252
0x1C [28]
D_REQ
Disable hardware request. If this flag is set, the eDMA hardware automatically
clears the corresponding EDMA_ERQL bit when the current major iteration count
reaches zero.
0 The channel’s EDMA_ERQL bit is not affected.
1 The channel’s EDMA_ERQL bit is cleared when the outer major loop is
complete.
Table 193. TCDn field descriptions (continued)
Bits
Word Offset
[n:n]
Field Name Description
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